EP0165986A1 - Systemes commandes par ordinateur - Google Patents

Systemes commandes par ordinateur

Info

Publication number
EP0165986A1
EP0165986A1 EP85900483A EP85900483A EP0165986A1 EP 0165986 A1 EP0165986 A1 EP 0165986A1 EP 85900483 A EP85900483 A EP 85900483A EP 85900483 A EP85900483 A EP 85900483A EP 0165986 A1 EP0165986 A1 EP 0165986A1
Authority
EP
European Patent Office
Prior art keywords
memory
information
data
bit
bits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP85900483A
Other languages
German (de)
English (en)
Inventor
Göran Anders Henrik HEMDAL
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hemdal Goeran Anders Hendrik
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of EP0165986A1 publication Critical patent/EP0165986A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
    • G06F11/106—Correcting systematically all correctable errors, i.e. scrubbing

Definitions

  • the invention relates to computer controlled systems and is particularly concerned with arrangements for improving memory securing and reliability of computer controlled systems.
  • the invention is applicable for example to a standard CPU.such as represented by Motorola MC 68000. INTEL 1APX 286, etc. and the memory accessed from this CPU, for instance to be included in a Master Control Unit.
  • the invention allows memory faults and spurious errors to be detected before a memory element is accessed by a normally executed instruction, thereby enabling preventive fault elimination.
  • the invention also allows a certain type of variable dynamic transposition of memory contents, thereby making meaningful interpretation of the memory contents impossible without knowledge of the correct key.
  • Each computer has at least one associated memory where information may be stored in binary form.
  • Figure 1 shows a typical computer consisting of a Central Processing unit (CPU) and a connected memory (M).
  • the memory is addressed via an Address Bus (ABUS) containing k address bits.
  • ABUS Address Bus
  • the memory itself contains 2k memory words, each one containing N information bits.
  • ADEC Address Bus Decoder
  • R Real Control Signal
  • DBUS Data Bus
  • the normal way of detecting and in certain cases, correcting spurious inadvertent errors is by providing redundancy in some form.
  • the N information bits in a memory word are therefore grouped into data bits which carry the actual information and redundancy bits, which are used only for error detection purposes as illustrated by Figure 2.
  • the redundancy bits may also be used for error correction purposes.
  • parity checking The simplest method of error detection by means of redundancy bits is the well known parity checking method, where a single redundancy bit, the so called parity bit is used.
  • the parity of a complete memory word is specified as odd or even. depending on whether the number of bits containing a one is odd or even. All memory words are thereby specified to have the same parity (i.e. either odd or even) when no error exists.
  • the parity bit can always be set so that, independently of the parity of the data bits, even parity for the total memory word is achieved. Any spurious single bit error or, in general, any odd number of bit errors will now show up as a parity error.
  • the parity bit may thus be used to detect spurious errors, but it cannot be used to localise or correct the errors, because any odd number of bit errors gives the same error indication. Also, parity checking does not give any error indication for an even number of bit errors.
  • the fault detection capability may be increased, even to the extent to obtain fault correction capabilities in certain cases. This is for instance the case with so called "Hamming" codes where multiple errors may be detected and single errors corrected.
  • the fault detection and -correction capability may be even more increased by increasing the number of redundancy bits to the same number as the data bits (duplication) .
  • errors may be found by means of a bit-by-bit comparison as illustrated in Figure 4, where comparison is indicated by 0.
  • SUBSTITUTE SHEET is obtained for the original data bits, assuming even parity. Thus the data bits are in error and the actual value should be taken from the redundancy bits. However, if an even number of bits are in error, then no parity indication will be obtained or even, if an odd number of bits are in error among the data bits and an odd number of bits are in error among the redundancy bits, thereby making the total number of errors even, both sides will indicate a parity error.
  • One class of error is the multiple bit error, where the pit pattern formed by the faulty bits happen to conform to a valid bit pattern. An example of this is the even number of bit errors by parity checking,
  • a second class of undetected errors is the "stuck" bit error where the actual value of the bit happens to be the value to bit isd "stuck" in. In this case the error will not be detected before the bit value is actually changed.
  • a scheme which might be utilized to detect "stuck" memory bits is to use a "refresh" routine, which cyclically scans through the memory, word by word and for each word reads the contents of the word, inverts these contents and writes them back, reads the contents a second time and rewrites the original contents into the memory word, the two read contents may now be compared whereby each bit of the first content must be different from the corresponding bit value of the second content. Any equality on the bit level indicates a "stuck" bit.
  • this method requires that the memory is locked for reading from any other process to prevent the temporarily inverted value from being read by anybody else than the "refresh” function, which significantly will increase the waiting times on the memory and thereby unacceptably reduce the performance of the total system.
  • the invention aims to improve the capability for off-line detection without introducing the drawbacks described above. Simultaneously the invention also offers a means of coding the information in memory so that this information cannot readily be interpreted without the aid of the invention.
  • Figure 5 illustrates the basic principle of the invention.
  • Each information word is associated with a number (M) of data bits, a number (P) of redundancy bits and a single Control Bit.
  • the information and redundancy bits have their conventional functions. The number of information and redundancy bits is not dependent on the invention.
  • the Control Bit determines how the information in memory is to be interpreted, so that one of the possible values of the Control Bit causes the information to be interpreted directly as is, while the opposite value cause the information to be inverted before interpretation. In the following it is assumed that the value "0" of the Control bit controls the direct interpretation.
  • the Control Bit In order for the use of the Control Bit to be meaningful, the Control Bit must be able to vary, preferably in a random or semi-random fashion.
  • One way of achieving this effect is to connect the Control Bit to a third gate G3, which inverts the Control Bit value each time the associated memory word is read. Hence, if the Control Bit is zero and the memory word is read, then the Control Bit is changed into a one. If now a new value is written into the memory word then the value will be physically written into the memory in inverted form, because the Control Bit now has the value "1". Writing of information into the memory has no effect on the value of the Control Bit.
  • FIG. 7 shows a possible realisation of the invention by means of a Master Control Unit (MCU) inserted between the Memory (M) and the CPU.
  • MCU Master Control Unit
  • Each physical memory word in the memory M contains its own data bits, redundancy bits and a single control bit according to the principle described with the aid of Figure 5.
  • the MCU contains three registers, a Data Bit Register (DBR), a Redundancy Bit Register (RBR) and a Control Bit Register (CBR) for temporary buffering of the data bits, the redundancy bits and the control bit respectively.
  • DBR Data Bit Register
  • RBR Redundancy Bit Register
  • CBR Control Bit Register
  • the MCU On recognizing the Read signal (R) the MCU asserts a Read Signal of its own to the memory (M), whereby the contents of the identified word (information bits D Q - D are transferred from the memory (M) to the MCU via the secondary data bus (DBUS2). On reception of the information the MCU buffers the
  • the CPU When information is to be written into the memory, then the CPU asserts the address in the same way as for reading, asserts the information bits to be written ( D ⁇ D N _ ⁇ ) on t ⁇ e Data Bus (DBUS) and asserts a Write (W) signal to the MCU.
  • the MCU On reception of this Write Signal the MCU first buffers the data bits into the DBR register and the redundancy bits into the RBR register. The CBR register is unaffected by this transfer. If, however, the current contents in CBR is a 1", then the information in DBR and RBR is again inverted by means of the gates G2R and G2D. No inversion occurs if CBR contains a "0". Finally the current contents of the three buffer registers CBR, RBR and DBR are transferred to the indicated word in the memory M as a result of the MCU asserting its own Write signal (W) to the memory.
  • W Write
  • this new refresh routine does not need to lock the memory for readout at any time during the refresh cycle, because the logic information read out from the memory will be the same regardless of whether it is physically stored in direct or in inverted form.
  • This new refresh routine is as such not the subject of the invention although the invention does form the basis of the refresh routine.
  • Figure 8 shows a different possible realisation of the invention.
  • the memory M is assumed to contain only data and redundancy bits within the control bits physically - ⁇ u -
  • CBM Control Bit Memory
  • FIG 8 has the advantage that it offers a simple means of encryption of the information held in the memory M, because the contents of the memory M cannot now be interpreted without the knowledge and existence of the key held in the CBM, provided that the redundancy bits in the memory are not dependent on the value of the associated control bit(s).
  • Figure 9 shows a possible arrangement for the utilisation of this additional capabaility of the invention.
  • an extra control signal (C) is used between the CPU and the MCU.
  • This control signal may be realised by any conventionally available technique, i.e. a direct signal, a code etc.
  • the Control Bit Memory is partitioned into two parts, one part (CBM) consisting of a read/write memory while the second part (10 ROM) consists of a read only memory.
  • Both the CBM and the 10 ROM part are accessed by means of the Address Decoder ADEC2.
  • the CBM part is, in Figure 9, associated with the memory addresses ) - (q - 1) and the 10 ROM part with the memory addresses q - 2k—1.
  • the addresses associated with the 10 ROM part are not critical for the invention, i.e. these addresses may specify any contiguous address range.
  • the part of the memory M accessed through the address codes associated with the 10 ROM is designated as the 10 BUFFER.
  • This 10 BUFFER and the associated 10 ROM are used as follows.
  • the 10 ROM contains a fixed bit pattern, which bit pattern is known to the manufacturer of the computer system, and which bit pattern may be different for each individual computer installation. Any software delivered by a manufacturer to a particular customer, for instance held on a diskette as shown in Figure 9, will contain the physical values of the data and redundancy bits for each memory word, assuming the actual values of the control bits held in the 10 ROM.
  • the CPU When loading the software on such a diskette by means of a suitable 10 Device (IODEV), then the CPU will transfer the information from the diskette to consecutive words of the 10 BUFFER area in the memory M by asserting the associated addresses on the Address Bus. When writing each word into the memory M the CPU asserts both the W and the C control signals. Assertion of the C signal causes the contents of the 10 ROM to be ignored, thereby ensuring that the contents of the diskette is directly transferred to the memory. When the entire contents of the diskette are transferred to the 10 BUFFER, or, if the software of the diskette exceeds the 10 BUFFER capacity, when the 10 buffer is full, the contents of the 10 buffer are now transferred to any convenient area in the memory M, this time without assertion of the control signal C. This ensures that the information will be correctly interpreted. After this transfer the 10 BUFFER is again available for transfer of the next part of the contents of the diskette as and when required.
  • IODEV 10 Device
  • this security feature does postulate that the assertion of the control signal C for any and all transfer of binary information to and from any external devices cannot by bypassed. This in turn required the existence of hardware priviledge levels in the CPUs, which already is a standard feature of most modern CPUs. It is finally to be noted that, although the basic principle of the invention utilises the logic operation inversion, it is by no means restricted to inversion only. Any other suitable type of logic or arithmetic operation may be used, for instance different types of permutation of the memory contents.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Detection And Correction Of Errors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Storage Device Security (AREA)

Abstract

Système d'ordinateur possédant une unité centrale, une mémoire de stockage d'information sous la forme binaire dans une pluralité d'éléments de données et une unité de commande principale exécutant des opérations arithmétiques/logiques sur les informations transférées entre l'unité centrale du processeur et la mémoire. Au moins quelques uns des éléments de la mémoire possèdent des organes servant à inverser de manière répétitive les informations contenues, afin de permettre de contrôler l'intégrité de l'élément de données. Afin de permettre à cette inversion de se poursuivre pendant des opérations normales de lecture et d'écriture des informations dans l'élément de données, celui-ci possède un chiffre supplémentaire de commande qui est inversé ou écrit sous une forme régulière avec les données principales stockées sur l'élément pour indiquer au dispositif lisant ou écrivant des informations dans l'élément de données si ce dernier se trouve dans sa forme régulière ou inversée.
EP85900483A 1983-12-21 1984-12-20 Systemes commandes par ordinateur Withdrawn EP0165986A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB8333984 1983-12-21
GB08333984A GB2158622A (en) 1983-12-21 1983-12-21 Computer controlled systems

Publications (1)

Publication Number Publication Date
EP0165986A1 true EP0165986A1 (fr) 1986-01-02

Family

ID=10553610

Family Applications (1)

Application Number Title Priority Date Filing Date
EP85900483A Withdrawn EP0165986A1 (fr) 1983-12-21 1984-12-20 Systemes commandes par ordinateur

Country Status (5)

Country Link
EP (1) EP0165986A1 (fr)
AU (1) AU3788185A (fr)
GB (1) GB2158622A (fr)
IT (1) IT1177492B (fr)
WO (1) WO1985002925A1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5699509A (en) * 1995-06-07 1997-12-16 Abbott Laboratories Method and system for using inverted data to detect corrupt data
US10545804B2 (en) 2014-10-24 2020-01-28 Sony Corporation Memory controller, memory system, and memory controller control method

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2036517B2 (de) * 1970-07-23 1972-10-19 Ibm Deutschland Gmbh, 7000 Stuttgart Verfahren zum betrieb eines schadhafte speicherelemente enthaltenden speichers fuer programmgesteuerte elektronische datenverarbeitungsanlagen
GB1344474A (en) * 1971-03-04 1974-01-23 Plessey Co Ltd Fault detection and handling arrangements for use in data proces sing systems
US3768071A (en) * 1972-01-24 1973-10-23 Ibm Compensation for defective storage positions
SE387764B (sv) * 1975-09-16 1976-09-13 Ericsson Telefon Ab L M Sett att upptecka fel i en minnesanordning och kategoritillempningslogik for utforande av settet
GB2099616A (en) * 1981-06-03 1982-12-08 Jpm Automatic Machines Ltd Improvements relating to microprocessor units
US4525599A (en) * 1982-05-21 1985-06-25 General Computer Corporation Software protection methods and apparatus
GB2122777A (en) * 1982-06-16 1984-01-18 Open Computer Services Limited Software protection apparatus and method
JPS59501128A (ja) * 1982-06-21 1984-06-28 エス・ピ−・エル・ソフトウエア・プロテクト・ア−・ゲ− デジタル情報コ−ド化方法および装置
EP0114522A3 (fr) * 1982-12-27 1986-12-30 Synertek Inc. Dispositif de protection de mémoire morte
GB8302096D0 (en) * 1983-01-26 1983-03-02 Int Computers Ltd Software protection in computer systems

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO8502925A1 *

Also Published As

Publication number Publication date
IT8424167A0 (it) 1984-12-21
GB2158622A (en) 1985-11-13
GB8333984D0 (en) 1984-02-01
IT1177492B (it) 1987-08-26
WO1985002925A1 (fr) 1985-07-04
AU3788185A (en) 1985-07-12

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Legal Events

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PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

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STAA Information on the status of an ep patent application or granted ep patent

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RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: HEMDAL, GOERAN ANDERS HENDRIK

18D Application deemed to be withdrawn

Effective date: 19851126