EP0186540B1 - Aus Dünnfilmtransistoren zusammengestellte elektronische Schaltung zur Steuerung einer Matrixeinrichtung - Google Patents

Aus Dünnfilmtransistoren zusammengestellte elektronische Schaltung zur Steuerung einer Matrixeinrichtung Download PDF

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Publication number
EP0186540B1
EP0186540B1 EP19850402238 EP85402238A EP0186540B1 EP 0186540 B1 EP0186540 B1 EP 0186540B1 EP 19850402238 EP19850402238 EP 19850402238 EP 85402238 A EP85402238 A EP 85402238A EP 0186540 B1 EP0186540 B1 EP 0186540B1
Authority
EP
European Patent Office
Prior art keywords
film transistors
transistors
matrix
register
thin film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
EP19850402238
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English (en)
French (fr)
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EP0186540A1 (de
Inventor
Francois Morin
Jacques Sergent
Stéphan Delaplace
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Ministere des Postes Telegraphes et Telephones
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Centre National dEtudes des Telecommunications CNET
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Application filed by Centre National dEtudes des Telecommunications CNET filed Critical Centre National dEtudes des Telecommunications CNET
Publication of EP0186540A1 publication Critical patent/EP0186540A1/de
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns

Definitions

  • the present invention relates to an electronic circuit formed of thin film transistors used to control a matrix device.
  • the invention relates to an electronic circuit of the shift register type used to sequentially control the rows or columns of a matrix device and in particular the rows or columns of a crystal display device liquids (flat screen with active matrix, screen for dashboard, ...), photosensitive video retinas with thin film transistors, optical sensors or rendering heads for fax systems with photodiodes lines, sensors, etc ...
  • an electronic memory formed by memory points distributed over the entire surface of the screen stores the video signal throughout the duration of the image.
  • An electro-optical transducer in particular a liquid crystal transducer, is in contact with each memory point and is excited throughout the duration of the image.
  • Each memory point is located at the intersection of a line and a connection column and it is made up of a thin-film transistor made on an insulating support and a capacitor of which the armatures are made, in the case where the transducer is a liquid crystal, by the electrodes of the liquid crystal cell itself, the insulating support constituting one of the two walls of said cell.
  • Each stage of the shift register generally comprises two elementary inverters and a capacitor used to store the video information.
  • each inverter is formed of at least two thin film transistors, arranged in cascade.
  • the thin-film transistors of the active matrix are generally produced with amorphous silicon, these have a low transconductance and a high input capacity, which leads to obtaining a limit operating frequency of the relatively low inverters and most of the time lower than the scanning frequency of the lines of a high complexity flat screen (300 to 500 lines).
  • shift registers of the charge transfer type such as the Bucket-Brigade-Device (BBD) or the Coupled-Charge-Device (CCD) in English terminology, less greedy in number of TCM, but the density of defects in amorphous silicon has led to ineffective charge transfer.
  • BBD Bucket-Brigade-Device
  • CCD Coupled-Charge-Device
  • the cost price of these screens is high due to the cost of the control circuits and the number of connections to be made between the flat screens and the corresponding circuits, or the number of welds to be made on the glass holder. It is generally accepted that the set of peripheral integrated circuits, that is to say the set of control circuits for the lines and the control circuits for the columns of the flat screen, represents half and even more than the price of total returns from said screen.
  • the subject of the present invention is precisely an electronic circuit formed of thin film transistors used to control matrix devices and in particular flat screens with active matrix making it possible to remedy the various drawbacks mentioned above.
  • peripheral integrated circuits With the active matrix while minimizing the cost of these circuits and therefore the overall price of flat screens by reducing the number of these peripheral circuits.
  • the subject of the invention is an electronic circuit, used to control the rows or columns of a matrix device, using on the one hand standard integrated circuits external to the device to perform the shift register function and on the other hand apart from thin-film transistors to provide the multiplexing function.
  • the invention relates to an electronic control circuit with N xn outputs used to control N xn rows or columns of a matrix device, and in particular of a matrix display device, characterized in that it comprises a multiplexing circuit, formed of N groups of n successive thin-film transistors, a first shift register with N outputs and a second shift register with n outputs, the gates of the n transistors of the same group being connected to the same output from the first register, to each group corresponding to a different output from said first register, the source of each transistor being connected to a different row or column, the drain of the i-th transistor of each group being connected to the i-th output of the second register, i being an integer such that 1 s isn.
  • matrix device can be understood a device comprising only one row or one column of components.
  • These electronic control circuits only comprise two external integrated circuits, which are the two shift registers, making it possible to supply, via the multiplexing circuit, Nxn lines or columns of a matrix device and in particular of a screen. active matrix dish. This therefore makes it possible to reduce the number of connections to be made between the external circuits and the flat screen as well as to reduce the cost price of these flat screens.
  • the electronic circuit of the invention When the electronic circuit of the invention is used to control the Nxn lines or the Nxn columns of a matrix device comprising thin film transistors produced on the same insulating support, the thin film transistors of the multiplexing circuit of the control circuit the invention can advantageously be produced on said support and simultaneously with the transistors of the matrix device.
  • FIG. 1 shows an electronic control circuit in accordance with the invention making it possible to control N xn lines of a flat screen with an active matrix, bearing the general reference 2.
  • This active matrix 2 is formed, in a conventional manner, of several conducting columns 4 and of N xn conducting lines denoted Lj, j being an integer ranging from 1 to N x n.
  • Lj N xn conducting lines
  • At each crossing of a column 4 and a line Lj is located a memory point 8 of the active matrix 2, formed of a thin film transistor 10 and a capacitor 12, connected in series.
  • This active matrix 2 further comprises N x n capacitors 14, one of the plates of each capacitor being connected to ground, the other to one of the conductive lines Lj of the matrix 2.
  • the control circuit of the N xn conductive lines Lj of the matrix 2 consists, on the one hand, of a multiplexing circuit, of general reference 16, consisting of N groups Gi, ..., G N thin-film transistors, each group G i comprising n successive transistors Ti, ... Tn, and on the other hand a first shift register 18, comprising N outputs, and a second shift register 20 comprising n outputs .
  • Such a control circuit makes it possible to considerably reduce the number of connections to be made between the control circuit and the active matrix, these connections being reduced to N + n connections instead of Nxn connections for the matrix devices of the prior art.
  • each conductive line Lj of the active matrix 2 is supplied by the source of a single thin film transistor; for example the source of the first transistor Ti of the group Gi is connected to the line Li, the source of the second transistor T 2 of the group G 1 is connected to the line L 2 and so on and the source of the last transistor T n of the group G N at line L N -n.
  • the gates of the N consecutive transistors T 1 , ... Tn of the same group Gi are connected to the same output P i of the first shift register 18, to each group corresponding to a different output P; of said first register.
  • the gates of the transistors T 1 , ... T n of the group Gi of transistors are all connected to the output P 1 of the first register 18, and the gates of the transistors T 1 , ... T n of the group G N transistors are all connected to the output P N of said first register 18.
  • the drains of the N xn thin-film transistors they are supplied so that the drain of the ith transistor Ti of each group Gi is connected to the ith output S i of the second register 20, i being an integer such that 1 1 i ⁇ n.
  • the first transistors denoted Ti of each group of transistors G 1 , ... G N are all connected to the first output Si of the second shift register 20, the second transistors T 2 of the groups of transistors G 1 , .. .G N are all connected to the output S2 of the second register 20, ... and the last transistors Tn of the groups Gi, ... GN of transistors are all connected to the last output S n of the second register 20.
  • the signal R (n) corresponds to the output signal of the shift register 20
  • the signal R (N) corresponds to the output signal of the shift register 18
  • the signal Li corresponds to the input signal of the first conductive line of the matrix 2.
  • Each pulse of duration ⁇ , delivered by the register 20, corresponds to the access time to a line conductive of the matrix, ⁇ being close to 64 ⁇ s and the pulse ⁇ ', delivered by register 18, is equal to nx ⁇ .
  • a voltage pulse ⁇ , delivered by the shift register 18 which operates at the scanning frequency of the lines of the flat screen, will only be transmitted to a line of said screen in the group G i made passing by the pulse ⁇ ' , provided by the shift register 18.
  • the corresponding lines of the flat screen are kept low thanks to the line capacitor 14 which remains charged for the duration of an image on the screen.
  • the transistors 10 of the active matrix 2 are thin film transistors produced on an insulating support such as glass, constituting in particular one of the two walls of the flat screen between which the liquid crystal is placed
  • the thin-film transistors of the multiplexing circuit 16 may advantageously be produced on said support and simultaneously with the manufacture of the transistors 10 of the active matrix 2 of the screen.
  • the two shift registers 18 and 20 will be standard integrated circuits, produced independently of the active matrix 2.
  • this manufacturing process consists in depositing, on an insulating support such as glass, constituting one of the walls of the flat screen, a transparent conductive layer in particular of tin and indium oxide and then a layer of n + doped amorphous silicon. These layers are then photo-etched using a first mask, so as to produce: the sources and drains of the thin-film transistors of the multiplexing circuit and of the matrix, one of the armatures of the capacitors 12 and 14, the conductive columns 4 of the matrix as well as the drain bus of the multiplexing circuit 16.
  • a layer of hydrogenated amorphous silicon is then successively deposited, an insulating layer, in particular of silicon oxide, and a conductive layer, for example of aluminum, then a photogravure of this stack of layers is carried out, using a second mask, so as to define the gate of the thin film transistors of the multiplexing circuit 16 and of the matrix 2 as well as the conductive lines Li of said matrix.
  • the assembly is then passivated using a deposit of a layer of silicon oxide for example, then openings are made in this passivation layer (by photoengraving using a third mask) , at the ends of the conductive lines of the matrix, on the grids of the thin film transistors of the multiplexing circuit 16 and on the drain bus of said multiplexing circuit.
  • a metallic deposit for example made of aluminum, is then produced, then this photo-etched with a fourth mask, in order to make the connections between the multiplexing circuit 16 and the active matrix 2, between the drain bus and the drains of the thin-film transistors of the multiplexing circuit and between the gates of the transistors T 1 , ... Tn of the same group Gi of transistors of the multiplexing circuit 16.
  • the circuit of the invention can advantageously be used to control the lines of a photosensitive video retina with thin film transistors; such a retina has in particular been described in French patent application FR-A 2 523 371 filed on March 10, 1982 in the name of the applicant and entitled "Photoconductive element made of hydrogenated amorphous silicon carbide and video retina cell using such an element".
  • the circuit of the invention can be used to control an array of photodiodes used in facsimile, these photodiodes and the thin film transistors of the multiplexing circuit being produced simultaneously on the same support.
  • circuit of the invention can be used to control any line of electronic components of the integrated transistor or diode type.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Liquid Crystal (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Electronic Switches (AREA)

Claims (2)

1. Elektronische Steuerschaltung mit N · n Ausgängen, die zur Steuerung von N · n Zeilen (Lj) oder Spalten (4) einer Matrixanordnung und insbesondere Zellen einer Matrixanzeigeeinrichtung (2) dienen, dadurch gekennzeichnet, daß sie enthält: eine Multiplexierschaltung (16) aus N Gruppen (G1,...GN) aus n hintereinendergeschalteten Dünnschichttransistoren (Ti,...Tn), ein erstes Schieberegister (18) mit N Ausgängen (P1,...PN) und ein zweites Schieberegister (20) mit n Ausgängen (S1,...Sn), wobei die Steuerelektroden der n Transistoren (T1,...Tn) einer selben Gruppe (Gi) mit einem selben Ausgang (Pi) des ersten Registers verbunden sind, einer jeden Gruppe (Gi) ein anderer Ausgang (P;) des ersten Registers (18) entspricht, die Sourceelektrode eines jeden Transistors mit einer anderen Zeile (Lj) oder Spalte (4) verbunden ist, die Drainelektrode des i-ten Transistors (Ti) einer jeden Gruppe (Gi) mit einem i-ten Ausgang des zweiten Registers (20) verbunden ist, wobei i eine ganze Zahl gemäss 1 ≤ i ≤ n ist.
2. Elektronische Schaltung nach Anspruch 1, die zur Steuerung von N · n Zeilen oder Spalten einer Matrixanordnung (2) dient, die aus Dünnschichttransistoren (10) besteht, die auf dem selben isolierenden Substrat ausgebildet sind, dadurch gekennzeichnet, daß die Dünnschichttransistoren (T1,...Tn) der Multiplexierschaltung (16) gleichzeitig mit den Transistoren (10) der Matrixanordnung auf dem Substrat ausgebildet sind.
EP19850402238 1984-11-28 1985-11-19 Aus Dünnfilmtransistoren zusammengestellte elektronische Schaltung zur Steuerung einer Matrixeinrichtung Expired EP0186540B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR8418110 1984-11-28
FR8418110A FR2573899B1 (fr) 1984-11-28 1984-11-28 Circuit electronique forme de transistors en couches minces pour commander un dispositif matriciel

Publications (2)

Publication Number Publication Date
EP0186540A1 EP0186540A1 (de) 1986-07-02
EP0186540B1 true EP0186540B1 (de) 1989-09-06

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EP19850402238 Expired EP0186540B1 (de) 1984-11-28 1985-11-19 Aus Dünnfilmtransistoren zusammengestellte elektronische Schaltung zur Steuerung einer Matrixeinrichtung

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EP (1) EP0186540B1 (de)
JP (1) JPS61198198A (de)
CA (1) CA1255406A (de)
DE (1) DE3572884D1 (de)
FR (1) FR2573899B1 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63316117A (ja) * 1987-06-19 1988-12-23 Fanuc Ltd 信号出力装置
US5510807A (en) * 1993-01-05 1996-04-23 Yuen Foong Yu H.K. Co., Ltd. Data driver circuit and associated method for use with scanned LCD video display
US6078318A (en) 1995-04-27 2000-06-20 Canon Kabushiki Kaisha Data transfer method, display driving circuit using the method, and image display apparatus
FR2776107A1 (fr) * 1998-03-10 1999-09-17 Thomson Lcd Procede d'affichage de donnees sur un afficheur matriciel
FR2776108B1 (fr) * 1998-03-10 2000-04-14 Thomson Lcd Procede d'affichage de donnees sur un afficheur matriciel

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5845035B2 (ja) * 1974-02-07 1983-10-06 日本電気株式会社 デンキヨクソウサホウシキ

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Publication number Publication date
CA1255406A (en) 1989-06-06
DE3572884D1 (en) 1989-10-12
FR2573899B1 (fr) 1986-12-26
EP0186540A1 (de) 1986-07-02
FR2573899A1 (fr) 1986-05-30
JPS61198198A (ja) 1986-09-02

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