EP0265643A2 - Verfahren und Einrichtung zur Verarbeitung von Bilddaten mit Bildanzeigesteuerfunktion - Google Patents

Verfahren und Einrichtung zur Verarbeitung von Bilddaten mit Bildanzeigesteuerfunktion Download PDF

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Publication number
EP0265643A2
EP0265643A2 EP87113351A EP87113351A EP0265643A2 EP 0265643 A2 EP0265643 A2 EP 0265643A2 EP 87113351 A EP87113351 A EP 87113351A EP 87113351 A EP87113351 A EP 87113351A EP 0265643 A2 EP0265643 A2 EP 0265643A2
Authority
EP
European Patent Office
Prior art keywords
image data
memory
display
memory area
processing apparatus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP87113351A
Other languages
English (en)
French (fr)
Other versions
EP0265643A3 (de
Inventor
Katsumi C/O Patent Division Kimoto
Masami C/O Patent Division Taoda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of EP0265643A2 publication Critical patent/EP0265643A2/de
Publication of EP0265643A3 publication Critical patent/EP0265643A3/de
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/14—Display of multiple viewports

Definitions

  • This invention relates to an image data processing apparatus and method with a display image control func­tion, and more particularly, to an image data processing apparatus and method capable of displaying plural types of superposed image data in a single-window manner or a multi-window manner.
  • the image data is stored in an optical memory, the stored image data is retrieved when necessary, and the re­trieved data is displayed on the CRT display.
  • This type of image data processing apparatus can display a single type or plural types of image data, read out of the optical memory through a page memory and a display memory, on the CRT display.
  • the old, or overlaid image data is erased from the display memory, and the new, or overlaying image data is written into the memory.
  • the overlaying image data is removed, to display the old image data again, that data must be read out of the page memory and written into the display memory. Therefore, a relatively long time is taken for the old image data to be displayed again.
  • Another object of this invention is to provide an image data processing apparatus and method, which solves the problem relating to the select and change time for the displayed image, and can instantaneously display the old image even if the displayed image is selectively changed.
  • an image data processing apparatus comprising first and second memory means for temporarily storing image data, means for displaying the image data stored in the first memory means, means for applying a command to selectively change and display part of the image data displayed on the displaying means, first control means for reading out the part of image data to be selectively changed and displayed, from the first memory means according to the command, and second control means for writing the part of image data read out by the first control means into the second memory means.
  • Fig. 1 shows a scheme of an image data processing apparatus.
  • CPU 11 executes the address-­controls to find an area in a bit map memory (to be described later) in the single-window display and the multi-window display, the area storing desired image data, and controls the operation of the overall image data processing apparatus.
  • This CPU 11 is connected to keyboard 13 for entering the command data, the retrieval data, and the like via system bus 12, magnetic memory device 15 for storing the retrieval data for optical memory device 14, and memory 16 for storing the program to control the operation of CPU 11, for example.
  • optical memory device 14 for the image data
  • page buffer memory 18 of a memory capacity of several pages of displayed image
  • display controller 19 to be described later
  • image controller 20 is connected to CRT display 21.
  • Display 21 displays the image data read out from optical memory device 14 and the image data read out from two-dimensional scanner 22.
  • Image controller 20 is connected to printer 23.
  • Priner 23 prints out the image data read out from optical memory device 14 and two-dimensional scanner 22.
  • Image controller 20 comprises an interface circuit for two-dimensional scanner 22 and printer 23, and a compress/extension circuit for compressing the image data (reducing redundancy), and for extending the same (restoring the reduced redundancy to the original state), and an elongation/reduction circuit.
  • Fig. 2 shows a scheme of display controller 19.
  • System bus 12 is coupled with controller 31 to execute the sequence control, and the control of data transfer.
  • Control section 31 is connected to first and second address generators 32 and 33. It is further connected to image bus controller 34 to control the read and write operation to image bus 17, and buffer circuit 35 con­nected to system bus 12.
  • First and second address generators 32 and 33 are independently operable. Each of the generators generates a given write address signal or a read-out address signal in accordance with an address supplied from CPU 11 through control section 31.
  • the address signals generated by first and second generators 32 and 33 are each appropriately selected by multiplexer 36, which is controlled by controller 31, and applied to bit map memory 37.
  • Bit map memory 37 has a memory capacity capable of storing the image data of several pages of displayed images.
  • the image data coming from through image bus 17 is stored into bit map 37, via data processor 39 including latch circuits, and the like.
  • the image data stored in bit map memory 37 is sequentially read out by the display address signal, which is output from CRT controller 40 and supplied through multiplexer 36.
  • the read out image data is supplied to CRT display 21, via drive circuit 41, which is controlled by CRT controller 40.
  • the image data which is contained in the area for image data B is read out from image data A.
  • the read out image data is stored in another memory area of bit map memory 37.
  • CPU 11 outputs the address data to indicate the location on the display screen of CRT display 21 in which image data B is to be displayed.
  • the address data is supplied to first address generator 32, via controller 31.
  • this generator generates the write address of image data B, i.e., the read out address for image data A corresponding to this image data B.
  • the address signal is supplied to bit map memory 37, via multiplexer circuit 36.
  • a RAS (row address strobe) signal, a CAS (column address strobe) signal, and a write signal W of bit map memory 37 are placed in a timing at time point T1, as shown in Figs. 5A to 5C. Further, bit map memory 37 is in a read mode.
  • an address signal supplied from first address generator 32 the image data A is read out from a memory area of bit map memory 37 into which the image data B is written.
  • the read out data (Fig. 5D) is latched in data processor 39.
  • write signal W is enabled.
  • image data B coming through image bus 17 from optical disc 17, for example is supplied through buffer circuit 38 to data processor 39, under control of image bus controller 34.
  • data processor 39 by the address signal generated from first address generator 32, the image data B is written into the memory area from which the image data in image data A is read out (W1 in Fig. 5D).
  • Ta indicates a period during first address generator 32 generates the address signal.
  • second address generator 33 generates an address signal for bit map memory 37 to write the image data, which has been latched in data processor 39.
  • This address signal is supplied to bit map memory 37, via multiplexer circuit 36.
  • write signal W is enabled.
  • the image data latched in data processor 39 is stored into the area of the bit map memory as specified by the address signal. See W2 in Fig. 5D.
  • To indicates the period during second address generator 33 generates the address signal.
  • image data B can be inserted, while the image data in the memory area corresponding to the image data B in image data A is being stored in another area of bit map memory 37.
  • first address generator 32 when image data B is being displayed overlaid on image data A, image data B is removed, as in the above case, first address generator 32 generates an address signal for reading out the image data stored in the other area of bit map memory 37. By this address signal, the image data is read out from bit map memory 37, and latched in data processor 39. Afterwards, an address signal for the area of the image B in image data A, is generated by second address generator 33. By the address signal, the image data latched by data processor 39 is written into image data A, and image data A is recalled. These image data processings in bit map memory 37 are performed during the fly-back period of CRT display 21.
  • Figs. 6 and 7 show the multi-window display opera­tion of the image data processing apparatus.
  • the spe­cific example to follow is the case of a display incorporating four-windows (211-214), and the case where a part of image data C already displayed on the second window 212 on the screen of CRT display 21 is displayed overlaid on a part A of image data A and B already displayed on the first window 211 on the screen of CRT display 21.
  • image data A is stored in the other area of memory 37.
  • the operation of Figs. 6 and 7 can be executed with the same manner that of Fig. 3.
  • the image data in the area on the screen into which another image data is inserted is not erased, but read out, and stored into the other area of bit map memory for display.
  • the image data stored in the other area of the display memory is recalled and written in the original area where the data was previously stored.
  • the selective change of display image in the single-window display and the multi-window display has been described.
  • This invention is not only applicable to the single-window display and the multi-window display, but also to the other types of display including the normal display.
  • the previous image data is read into the other memory area after it is read; when the previous display image is recalled, it is written into the original memory area.
  • the function essentially required for the image data processing apparatus with display image control function according to this invention is only to save the original image data, not to erase it in the display memory. Other functions may be used in combina­tion with the above function, when necessary.
  • an image data processing apparatus and method having a display image control function to save the image data to be selected and changed in a specific area on the screen, and not to erase it in the display memory.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Digital Computer Display Output (AREA)
  • Image Processing (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Ultra Sonic Daignosis Equipment (AREA)
EP87113351A 1986-10-31 1987-09-11 Verfahren und Einrichtung zur Verarbeitung von Bilddaten mit Bildanzeigesteuerfunktion Withdrawn EP0265643A3 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP61258512A JP2507361B2 (ja) 1986-10-31 1986-10-31 画像情報処理装置
JP258512/86 1986-10-31

Publications (2)

Publication Number Publication Date
EP0265643A2 true EP0265643A2 (de) 1988-05-04
EP0265643A3 EP0265643A3 (de) 1990-08-22

Family

ID=17321240

Family Applications (1)

Application Number Title Priority Date Filing Date
EP87113351A Withdrawn EP0265643A3 (de) 1986-10-31 1987-09-11 Verfahren und Einrichtung zur Verarbeitung von Bilddaten mit Bildanzeigesteuerfunktion

Country Status (2)

Country Link
EP (1) EP0265643A3 (de)
JP (1) JP2507361B2 (de)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0431618A3 (en) * 1989-12-06 1991-10-23 Kabushiki Kaisha Toshiba Method and apparatus for multiwindow display with enhanced window manipulation facilities
EP0647931A3 (de) * 1993-08-13 1995-07-19 Firstperson Inc Verfahren und Einrichtung zum Erstellen eines Rasterpufferspeichers mit schnellen Kopiermitteln.
US5905483A (en) * 1992-01-30 1999-05-18 Canon Kabushiki Kaisha Display control apparatus
EP0671719B1 (de) * 1994-03-08 2001-11-21 Texas Instruments Incorporated Übertragungsprozessor mit Transparenz
GB2369760A (en) * 2000-09-26 2002-06-05 Samsung Electronics Co Ltd Multimedia display for a mobile terminal

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007170279A (ja) * 2005-12-22 2007-07-05 Aisin Seiki Co Ltd 内燃機関の吸気装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5891492A (ja) * 1981-11-27 1983-05-31 株式会社日立製作所 画像表示装置の制御方式
JPS59116787A (ja) * 1982-12-24 1984-07-05 株式会社日立製作所 デイスプレイ表示方式
IL71925A (en) * 1984-05-25 1991-03-10 Elscint Ltd Split-screen imaging
JPS60251431A (ja) * 1984-05-29 1985-12-12 Matsushita Electric Ind Co Ltd メモリ表示装置
JPS60257488A (ja) * 1984-06-01 1985-12-19 株式会社ピーエフユー 表示制御装置
CA1233257A (en) * 1984-12-26 1988-02-23 Irene H. Hernandez Tailored document building

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0431618A3 (en) * 1989-12-06 1991-10-23 Kabushiki Kaisha Toshiba Method and apparatus for multiwindow display with enhanced window manipulation facilities
US5430838A (en) * 1989-12-06 1995-07-04 Kabushiki Kaisha Toshiba Method and apparatus for multi-window display with enhanced window manipulation facilities
US5905483A (en) * 1992-01-30 1999-05-18 Canon Kabushiki Kaisha Display control apparatus
EP0647931A3 (de) * 1993-08-13 1995-07-19 Firstperson Inc Verfahren und Einrichtung zum Erstellen eines Rasterpufferspeichers mit schnellen Kopiermitteln.
US5512918A (en) * 1993-08-13 1996-04-30 Sun Microsystems, Inc. High speed method and apparatus for generating animation by means of a three-region frame buffer and associated region pointers
EP0671719B1 (de) * 1994-03-08 2001-11-21 Texas Instruments Incorporated Übertragungsprozessor mit Transparenz
GB2369760A (en) * 2000-09-26 2002-06-05 Samsung Electronics Co Ltd Multimedia display for a mobile terminal
GB2369760B (en) * 2000-09-26 2003-03-19 Samsung Electronics Co Ltd Screen display apparatus for a mobile terminal
US7057621B2 (en) 2000-09-26 2006-06-06 Samsung Electronics Co., Ltd. Screen display apparatus and a method for utilizing the screen display apparatus in a mobile terminal

Also Published As

Publication number Publication date
JP2507361B2 (ja) 1996-06-12
EP0265643A3 (de) 1990-08-22
JPS63113725A (ja) 1988-05-18

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