EP0267730A2 - Wolfram Metallisierung - Google Patents

Wolfram Metallisierung Download PDF

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Publication number
EP0267730A2
EP0267730A2 EP87309737A EP87309737A EP0267730A2 EP 0267730 A2 EP0267730 A2 EP 0267730A2 EP 87309737 A EP87309737 A EP 87309737A EP 87309737 A EP87309737 A EP 87309737A EP 0267730 A2 EP0267730 A2 EP 0267730A2
Authority
EP
European Patent Office
Prior art keywords
tungsten
glue layer
dielectric
layer
recited
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP87309737A
Other languages
English (en)
French (fr)
Other versions
EP0267730A3 (en
EP0267730B1 (de
Inventor
Lowell Henry Holschwandner
Virendra Vir Singh Rana
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
American Telephone and Telegraph Co Inc
AT&T Corp
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Filing date
Publication date
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Application filed by American Telephone and Telegraph Co Inc, AT&T Corp filed Critical American Telephone and Telegraph Co Inc
Publication of EP0267730A2 publication Critical patent/EP0267730A2/de
Publication of EP0267730A3 publication Critical patent/EP0267730A3/en
Application granted granted Critical
Publication of EP0267730B1 publication Critical patent/EP0267730B1/de
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/412—Deposition of metallic or metal-silicide materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/042—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers
    • H10W20/045—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers for deposition from the gaseous phase, e.g. for chemical vapour deposition [CVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches

Definitions

  • This invention relates to metallization used in semiconductor devices.
  • the dimensions of the components of the integrated circuits continue to decrease. Not only do device dimensions decrease, but the dimensions of the interconnects, that is, the lines and windows used to connect devices decrease.
  • the windows are often termed vias by those skilled in the art. It is noted that the term window is sometimes applied only to the openings to the source, gate, or drain electrodes while the term via is applied to the opening between levels in multilevel metal structures.
  • the use of high temperature thermal processing to taper the vias by causing a dielectric material to flow eventually becomes impossible as the via dimensions decrease. Consequently, the vias that must be filled with metal not only have a high aspect ratio, that is, a high ratio of height to width, but their walls are also substantially vertical.
  • Aluminum is difficult to deposit uniformly in such vias and poor step coverage results for conventional deposition techniques such as sputtering. This not only leads to possible discontinuities in the metal coverage but also makes planarization of the surface, frequently required for subsequent processing such as second level metallization, very difficult.
  • LPCVD tungsten is a desirable alternative because it has a conformal step coverage.
  • LPCVD tungsten also offers advantages for use as interconnects. Besides having conformal step coverage, it has high electromigration resistance, resistance to hillock formation and high temperature stability. Although many methods of depositing LPCVD tungsten have been proposed, they are all included within two generic categories which are conveniently termed selective and blanket.
  • Selective deposition typically relies upon the reaction of a gas, such as tungsten hexafluoride, with substrates, such as silicon, to leave tungsten on the silicon surface. Selective deposition is also possible on metals and silicides.
  • a gas such as tungsten hexafluoride
  • substrates such as silicon
  • tungsten is deposited over the entire surface and then etched back so that tungsten ideally remains only in the vias or as, for example, interconnects. While this process is conceptually simple, tungsten does not adhere well to silicon dioxide and practical problems arise. For example, after the deposition has been completed, the tungsten film may simply peel off the silicon dioxide which is also an obviously undesirable result.
  • a glue layer is a layer of material deposited prior to the tungsten and which has good adhesion both to the underlying dielectric layer and to the tungsten.
  • Several substances have been proposed for glue layers.
  • the use of both elemental metals, such as Ti, and metallic silicides, such as WSi2 has been proposed. See, for example, Comparison of Two Contact Plug Techniques for Use with Planarized Oxide and A Contact Filling Process with CVD-Tungsten for Multilevel Metallization Systems, Proceedings of the V-MIC Conference, pp. 403-410, and pp. 443-449, June 9-10, 1986, respectively.
  • the use of a thick glue layer is undesirable because during the etch back step, severe undercutting of the tungsten layer occurs if, as is often the case, the glue layer etches more rapidly than does the tungsten.
  • the undercutting may make subsequent processing very difficult. For example, voids may be left in the oxide and in subsequent metallizations after metal deposition.
  • the glue layer material should be electrically conducting. Only metals or silicides have been proposed as glue layer materials because of the rapid film growth in these materials. However, the use of some metals, such as aluminum, has not been seriously considered because a thick aluminum layer may cause spiking due to its rapid diffusion into the underlying material. Other conducting compounds have not yet been proposed as glue layers.
  • tungsten can be blanket deposited with good adhesion over a dielectric covering a portion of a silicon surface by first depositing a film comprising either Al or a conducting nitride such as TiN as a glue layer.
  • the glue layer film may be deposited, through openings in the dielectric, directly on the silicon or on a conducting material, such as a silicide, overlying the silicon.
  • the glue layer is also deposited on the dielectric.
  • Both TiN and Al films provide good adhesion down to thicknesses as small as approximately 3 nm. The minimum thickness is determined primarily by the requirement that the entire wafer surface be covered adequately.
  • the thinner glue layers are generally preferred as they minimize any problems that might be caused by either spiking of deposited metal or undercutting during reactive sputter etching (RSE).
  • RSE reactive sputter etching
  • a thicker layer of TiN may be used.
  • the Al layer is typically less than 25 nm thick although the maximum thickness will be determined by device design and processing parameters. Uses other than plugs are contemplated. In particular, interconnects and gate structures are also contemplated.
  • Fig. 1 is a schematic representation of a tungsten metallization according to this invention. Depicted are silicon layer 1, dielectric region 3, glue layer 5 and tungsten metallization 7. As can be seen, the glue layer and metallization extend into a via 9. The glue layer covers the interior surface of the via as well as the underlying silicon layer 1. The glue layer also covers the dielectric region 3. It will be readily appreciated that the individual components of the integrated circuit are not depicted for reasons of clarity.
  • the vias are formed by conventional VLSI processing steps which deposit, pattern and etch the dielectric, etc. These steps are well known to those skilled in the art and need not be described in detail.
  • the dielectric region depicted comprises SiO2 although it will be appreciated by those skilled in the art that other dielectric materials may be used. For example, B and P doped SiO2 and Si3N4 might be used. It will also be appreciated that although layer 1 is described as silicon, other conducting materials might be used. For example, conducting silicides might be used. Such silicides are formed on the silicon surface.
  • the glue layer is described as being deposited over a silicon surface, the presence of other materials between the glue layer and the silicon surface is contemplated.
  • the glue layer is expediently deposited by well known techniques such as sputtering.
  • the glue layer comprises at least one material selected from the group consisting of Al and conducting nitrides such as TiN. It will be appreciated that minor amounts of other materials may be present in the glue layer. For example, either or both Si and Cu may be present in Al. These materials are metallurgically stable with respect to the tungsten film. Good adhesion, as evidenced by an inability to remove the film by pulling on an attached adhesive tape, is obtained down to glue layer thicknesses of approximately 3 nm.
  • the native oxides on TiN and Al2O3 are thin. Although the successful use of Al might seem surprising in view of its strong susceptibility to oxide formation, it is believed that during the tungsten deposition most of the aluminum oxide present is removed although residues of non-conductive fluorides may remain. To prevent spiking, the Al layer should be less than approximately 25 nm thick. However, as will be readily appreciated by those skilled in the art, a precise maximum thickness cannot be given as it depends on several factors. These factors include the desired junction depth and the post Al deposition processing parameters. Given these factors, one skilled in the art can readily determine the maximum Al thickness.
  • pinholes in the glue layer need not be a significant problem. That is, the presence of some pinholes will not necessarily adversely affect the adhesive properties sought. It must also be remembered that, within the vias, pinholes are not significant as the electrical contact will still be formed if W goes through a pinhole at the bottom of the via provided that there is no chemical interaction with the substrate. For example, W interaction with, e.g., TiS2, is not a problem. However, pinholes may be a problem for the W/Si interface although the interaction of W with a small amount of silicon can generally be tolerated. No adverse results occurs if the W touches the dielectric through a pinhole.
  • the growth of W films on the nitrides is surprising because it is hypothesized there are no displacement reactions which provide W nuclei for further film growth, i.e., the nitrides do not reduce WF6.
  • the Ti-N bonds are sufficiently strong so that the interaction of Ti with WF6 is not energetically favored.
  • the growth of W films on the nitride is believed to occur by the reduction of WF6 with H2, solely. Upon exposure to WF6 and H2, H and F atoms react and nucleate W on the surface. After the resulting islands coalesce, the growth rate of films is similar to the rates on Si or Al coated surfaces.
  • the disadvantage of using a displacement reaction is that fluorides are formed at the interface.
  • Fig. 2 depicts a via after etching.
  • Conventional etching techniques can be used for the etching steps. It should be remembered that the tungsten layer is typically overetched to guarantee its complete removal from areas not covered with resist in case there are non-uniformities in layer thickness. The overetch not only removes the tungsten but removes the thin glue layer contacting layer 1 without the need for any additional etching chemistry.
  • TiN ideally suited for use as a glue layer with etch-back plugs and interconnects.
  • Fig. 3 is useful in explaining interconnect fabrication. Numerals identical to those used in Fig. 1 represent identical elements. Also depicted is patterned resist 11. To form interconnects, the tungsten and glue layers depicted are etched and the resist removed to yield the structure shown in Fig. 4. An Al layer under W interconnects should provide low resistance contacts. The use of Al is particularly suited for upper levels in multilevel metallization schemes where junction spiking is not a consideration. Also, it is suitable for very thin Al glue layers on Si contacts, as well as silicided junctions, where junction spiking may not occur.

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
EP87309737A 1986-11-10 1987-11-04 Wolfram Metallisierung Expired - Lifetime EP0267730B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US92904386A 1986-11-10 1986-11-10
US929043 1986-11-10

Publications (3)

Publication Number Publication Date
EP0267730A2 true EP0267730A2 (de) 1988-05-18
EP0267730A3 EP0267730A3 (en) 1988-10-19
EP0267730B1 EP0267730B1 (de) 1992-03-18

Family

ID=25457230

Family Applications (1)

Application Number Title Priority Date Filing Date
EP87309737A Expired - Lifetime EP0267730B1 (de) 1986-11-10 1987-11-04 Wolfram Metallisierung

Country Status (3)

Country Link
EP (1) EP0267730B1 (de)
JP (1) JP2770945B2 (de)
DE (1) DE3777538D1 (de)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4851369A (en) * 1987-12-04 1989-07-25 U.S. Philips Corporation Method of establishing a structure of electrical interconnections on a silicon semiconductor device
EP0357221A1 (de) * 1988-08-01 1990-03-07 AT&T Corp. Verfahren zum Herstellen von Kontakten aus flache Übergänge enthaltenden integrierten Schaltungen
US4999317A (en) * 1989-09-29 1991-03-12 At&T Bell Laboratories Metallization processing
US5008216A (en) * 1988-10-03 1991-04-16 International Business Machines Corporation Process for improved contact stud structure for semiconductor devices
US5084415A (en) * 1989-10-23 1992-01-28 At&T Bell Laboratories Metallization processing
US5149672A (en) * 1988-08-01 1992-09-22 Nadia Lifshitz Process for fabricating integrated circuits having shallow junctions
US5192703A (en) * 1991-10-31 1993-03-09 Micron Technology, Inc. Method of making tungsten contact core stack capacitor
US5225372A (en) * 1990-12-24 1993-07-06 Motorola, Inc. Method of making a semiconductor device having an improved metallization structure
US5411903A (en) * 1990-09-28 1995-05-02 Motorola, Inc. Self-aligned complementary HFETS
US5760475A (en) * 1987-03-30 1998-06-02 International Business Machines Corporation Refractory metal-titanium nitride conductive structures

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3616401A (en) * 1966-06-30 1971-10-26 Texas Instruments Inc Sputtered multilayer ohmic molygold contacts for semiconductor devices
JPS5950544A (ja) * 1982-09-17 1984-03-23 Hitachi Ltd 多層配線の形成方法
JPS6043858A (ja) * 1983-08-22 1985-03-08 Toshiba Corp 半導体装置の製造方法
JPS61112353A (ja) * 1984-11-07 1986-05-30 Nec Corp 多層配線の形成方法
JPS61208241A (ja) * 1985-03-13 1986-09-16 Matsushita Electronics Corp 半導体装置の製造方法
GB2181456B (en) * 1985-10-07 1989-10-25 Gen Electric Depositing metal films on dielectric substrates
JPS62206852A (ja) * 1986-03-07 1987-09-11 Agency Of Ind Science & Technol 半導体装置の製造方法

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5760475A (en) * 1987-03-30 1998-06-02 International Business Machines Corporation Refractory metal-titanium nitride conductive structures
US4851369A (en) * 1987-12-04 1989-07-25 U.S. Philips Corporation Method of establishing a structure of electrical interconnections on a silicon semiconductor device
EP0357221A1 (de) * 1988-08-01 1990-03-07 AT&T Corp. Verfahren zum Herstellen von Kontakten aus flache Übergänge enthaltenden integrierten Schaltungen
US5149672A (en) * 1988-08-01 1992-09-22 Nadia Lifshitz Process for fabricating integrated circuits having shallow junctions
US5008216A (en) * 1988-10-03 1991-04-16 International Business Machines Corporation Process for improved contact stud structure for semiconductor devices
US4999317A (en) * 1989-09-29 1991-03-12 At&T Bell Laboratories Metallization processing
EP0420529A3 (en) * 1989-09-29 1993-07-14 American Telephone And Telegraph Company Metallization processing
US5084415A (en) * 1989-10-23 1992-01-28 At&T Bell Laboratories Metallization processing
EP0425147A3 (en) * 1989-10-23 1993-06-30 American Telephone And Telegraph Company Metallization processing
US5411903A (en) * 1990-09-28 1995-05-02 Motorola, Inc. Self-aligned complementary HFETS
US5225372A (en) * 1990-12-24 1993-07-06 Motorola, Inc. Method of making a semiconductor device having an improved metallization structure
US5192703A (en) * 1991-10-31 1993-03-09 Micron Technology, Inc. Method of making tungsten contact core stack capacitor

Also Published As

Publication number Publication date
JPS63133648A (ja) 1988-06-06
DE3777538D1 (de) 1992-04-23
EP0267730A3 (en) 1988-10-19
JP2770945B2 (ja) 1998-07-02
EP0267730B1 (de) 1992-03-18

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