EP0329151A2 - Digitale Signalverarbeitungsvorrichtung - Google Patents

Digitale Signalverarbeitungsvorrichtung Download PDF

Info

Publication number
EP0329151A2
EP0329151A2 EP89102717A EP89102717A EP0329151A2 EP 0329151 A2 EP0329151 A2 EP 0329151A2 EP 89102717 A EP89102717 A EP 89102717A EP 89102717 A EP89102717 A EP 89102717A EP 0329151 A2 EP0329151 A2 EP 0329151A2
Authority
EP
European Patent Office
Prior art keywords
data
signal processing
block
memory
digital signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP89102717A
Other languages
English (en)
French (fr)
Other versions
EP0329151A3 (de
Inventor
Tokumichi Mitsubishi Denki K.K. Murakami
Koh Mitsubishi Denki K.K. Kamizawa
Naoto Mitsubishi Denki K.K. Kinjo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP63037921A external-priority patent/JPH01211162A/ja
Priority claimed from JP63063695A external-priority patent/JPH01237838A/ja
Priority claimed from JP63298722A external-priority patent/JPH02145079A/ja
Priority claimed from JP63298723A external-priority patent/JPH02145077A/ja
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to EP95114932A priority Critical patent/EP0690376B1/de
Priority to EP95114933A priority patent/EP0703533B1/de
Priority to EP95114934A priority patent/EP0690377B1/de
Publication of EP0329151A2 publication Critical patent/EP0329151A2/de
Publication of EP0329151A3 publication Critical patent/EP0329151A3/de
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • G06F9/505—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering the load
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5061—Partitioning or combining of resources
    • G06F9/5066—Algorithms for mapping a plurality of inter-dependent sub-tasks onto a plurality of physical CPUs
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00—Image analysis
    • G06T7/20—Analysis of motion
    • G06T7/223—Analysis of motion using block-matching
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/43—Hardware specially adapted for motion estimation or compensation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/43—Hardware specially adapted for motion estimation or compensation
    • H04N19/433—Hardware specially adapted for motion estimation or compensation characterised by techniques for memory access
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/50—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
    • H04N19/503—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving temporal prediction
    • H04N19/51—Motion estimation or motion compensation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
    • H04N19/61—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2207/00—Indexing scheme for image analysis or image enhancement
    • G06T2207/10—Image acquisition modality
    • G06T2207/10016—Video; Image sequence
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/30—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using hierarchical techniques, e.g. scalability

Definitions

  • the present invention relates to a digital signal processing apparatus which performs computational processes for digital signals.
  • Fig. 1 shows the multiprocessor system described in article entitled "A Real Time Video Signal Processor Suitable for Motion Picture Coding Applications", IEEE, GLOBCOM '87, p. 453.
  • input data 1 is received by a data transfer controller 3, and thereafter data 4 are transferred selectively to digital signal processors 2, i.e. DSP-1 through DSP-N, in block-1.
  • digital signal processors 2 i.e. DSP-1 through DSP-N
  • resultant data 5 is transferred to block-2 and processed by respective DSPs for the next processing step.
  • Fig. 2(a) shows divided memory areas of the DSPs.
  • shown here is an example of parallel processing using three DSPs 2, to which process areas A, B and C are assigned evenly.
  • the volume of computation needed for the process differs depending on the valid pixel rate even though the number of pixels in the process area is constant.
  • the volume of computation or computation time needed is proportional to the valid pixel rate.
  • the conventional digital signal processing apparatus arranged as described above has its overall process time determined from the longest process time among DSPs when the density of information, such as the valid pixel rate, within a frame is uneven and the distribution of information varies with time, resulting in a degraded process efficiency per DSP unit.
  • Fig. 3 is a diagram showing, as an example, the arrangement of other digital signal processing apparatus disclosed in an article entitled "Realtime Video Signal Processor Module", in the proceeding of ICASSP '87, pp. 1961 - 1964, April 1987, Dallas, U.S.A.
  • 1 an input terminal
  • 4 is an input bus for distributing input data on the input terminal
  • 28a is a feedback bus for distributing the result of previous process
  • 20 are signal processing modules each including an input storage 21, a processing unit 22, an output storage 23 and a timing control unit 24.
  • 260 is a local decoder which receives the coding parameter 255
  • 261 is an inter frame adder
  • 262 is an in-loop filter
  • 263 is a coding frame memory
  • 264 is previous coded frame data
  • 265 is a motion compensator
  • 266 is current frame data fed from the input frame buffer 251 to the motion compensator 265,
  • 267 is motion vector data
  • 268 is compensated previous frame data fed from the motion compensator 265 to the inter-frame subtracter 252 and inter-frame adder 261
  • 269 is a feedback signal
  • 270 is a coding controller which provides coding control information for the video multiplexer 257, a feed-forward signal to the input frame buffer 251, a block identification control signal 273 to the block identifier 253, and a coding control signal 274 to the variable-length coder 256.
  • This digital signal processing apparatus is principally based on the foregoing area division parallel processing, and is intended such that each signal processing module 20 deals with a divided frame area independently on a realtime basis.
  • the digital signal processing apparatus is intended for the achievement of a coder as shown in Fig. 5, only portions excluding the variable-length coder 256, video multiplexer 257, transmission buffer 258 and coding controller 270 can be realized. Namely, it is not suitable for a continuous process in one video frame, and is limited to the inter-frame coding loop process ranging from the input frame buffer 251 to the block identifier 253, coder 254, local decoder 260, coding frame memory 263, and to the motion compensator 265 useful for data completely divisible within a frame.
  • the conventional digital signal processing apparatus arranged as described above have the following problems for processing video signals.
  • Fig. 7 shows the sequence of process for implementing the 3-input operation of the form of expression (1) by the digital signal processing system, for example, shown in Fig. 6.
  • step ST3 the data address generator 32 sets up the starting addresses of the data set C and data set ai ⁇ bi, and ci data is read out of the 2P-RAM 31 to the register 36.
  • the selector 35 selects the data bus to load the data of ai ⁇ bi in the external memory 47 into the register 37.
  • step ST4 needs to expend two cycles of useless command reading for the external memory in advance.
  • the motion compensation process is to calculate for the input signal 1 the amount of distortion between a 11-by-12 block located in a specific position in the current frame shown in Fig. 9(A) and M pieces of blocks in the search range S in the previous frame shown in Fig. 9(B) to evaluate the position of the block y providing a minimal distortion relative to the position of the input block, i.e., motion vector V, and to recognize the signal of the minimal distortion block as a prediction signal.
  • Fig. 10 shows the sequence of operations for detecting the motion vector V.
  • the present invention is intended to overcome the foregoing prior art deficiencies, and a prime object to provide a digital signal processing apparatus which uses the multiprocessor parallel configuration to its maximal processing ability.
  • a further object of this invention is to provide a motion compensative operation method which, in constructing the motion compensator of an image coding system with a digital signal processing apparatus, requires less number of parallel processors, thereby enhancing the simplicity and compactness of the hardware structure.
  • the inventive digital signal processing apparatus comprises a first through third data reading address generators adapted to read three independent data sets independently and simultaneously, and a pair of arithmetic unit and multiplier adapted to execute a 3-input-1-output arithmetic operation at high speed by receiving the output of counterpart mutually.
  • the inventive motion compensation method using a digital signal processing apparatus divides a current input frame of digital image data, which consists of a plurality of frames, entered successively into a plurality of blocks, searches the previous input frame for a pattern which resembles the block of the input frame, and implements a coding process with a block of minimal distortion in highest resemblance as a prediction signal, wherein in detecting a block of minimal distortion through the computation of inter-pattern resemblance using the difference and cumulation of pixels in each block between the block of the current input frame and blocks of M in number (M is a positive integer) in the previous input frame, the method uses, for the pattern resemblance computation, a maximum of K pieces of pixels (K is an integer greater than 0 and less than or equal to a total number of pixels in a block), implements an intermediate check n times (n is an integer greater than 0) during the computation of resemblance at time points when the number of reference pixels is smaller than K, skips the computation for remaining pixels when
  • Fig. 11 shows, as an embodiment of this invention, an example of the image coder of the digital signal processing apparatus.
  • input data 1 is entered to a first through third input memories 6.
  • a task controller 7 estimates the number of valid pixels on the basis of the contents of the input memory 6, determines the distribution of coding process among a first, second and third DSPs 2, and issues control signals as address control signals 8 to the DSPs 2.
  • the first, second, and third DSPs 2 issue addresses 9 to respective first, second and third input memories 6 to fetch data 10 assigned for processing, and implement the coding processes based on the preset program.
  • the first, second and third DSPs 2 store processed data in an output memory 11, which, after reading the whole data of the DSP block, sents the processed data to the next DSP block.
  • each DSP 2 is controlled by the task controller 7 so that all DSP 2 have even numbers of valid pixels assigned, and therefore the image coding process time is controlled so that the difference of process times among the DSPs 2 is minimal.
  • the task controller 7 issues the address control signals 8 corresponding to the assignment distribution to the first, second and third DSPs 2.
  • the first DSP 2 in response to the issuance of the address control signal 8 for coding the image data of area A to the first DSP 2, it produces the address 9 for the area A′ in the first input memory 6 to fetch data and implements the image coding process by following the prescribed program.
  • the second and third DSPs 2 are directed to carry out the image coding processes for the areas B′ and C′, respectively. Consequently, the first, second and third DSPs 2 have their numbers of valid pixels EA′, EB′ and EC′ for coding virtually made even, i.e., the same quantity of image data to be processed, as shown in Fig. 12(b).
  • the maximum volume of process M′ dealt with by the inventive apparatus becomes sufficiently less than that M of the conventional apparatus, and the process time required for each DSP block is reduced.
  • the scanning period shall be the number of parallelness times of the input cycle of the signal process block, and when a series processing is to be done the scanning period shall be 1/n of the input cycle; thus by the synchronization with the input data frame (for example a video frame) the matching with the real time can be maintained.
  • Fig. 16 shows an example of the internal constitution of the signal processor elements 318 as shown in Fig. 15.
  • 330 is a terminal to which the common bus input/output port 316 is to be connected;
  • 331 is a terminal to which the interruption control port 317 is to be connected;
  • 332 is a terminal to which the buses 314 and 315 are to be connected;
  • 333 is similarly a terminal which connects the buses 314 and 315 between the adjacent signal processors;
  • 334 is an external bus control section (BUS-CONT) with the function as a competitive control means to control the make/break of the common bus 305 through the bus 316;
  • 335 is a bus for loading a writable control storage (W C S) 336, which memorizes a signal processing program, from the external bus control section 334 at an initial time;
  • 337 is a BUSREQ which requires the connection of the common bus 305 to the external bus control section 334;
  • 338 is a BUSACK which
  • Fig. 17 explains the internal control operation of the digital signal processing apparatus shown in Fig. 15, and the same parts as those shown in Fig. 15 are given the same symbols; the explanation of them is therefore omitted.
  • Input data 311 digitized by an A/D converter 310 are memorized in an input frame buffer 313 being scanned in a raster form in synchronization with a video frame synchronizing signal 6, for example.
  • Input data 311 memorized in the input frame buffer 313 are added to initial parameter data 302 by the data flow control section 301 by blocks and the parameter data 302 are memorized in the parameter memory 312.
  • These parameter memory 312 and input frame buffer 313 consist of dual port memories and writing/reading is simultaneously possible between two independent ports.
  • Data blocks are read from the input frame buffer 313, and the parameter is read in a data block unit from the parameter memory 312.
  • Data blocks and parameter are sent through the buses 314 and 315 to the signal processor 318 element where they are given the first process of a series of functional processes in a block unit.
  • the results and the rewritten parameters are written in the dual port memory 349 in the signal processor element 318. It is the basic function of a processor module 320 to execute processes successively between the adjacent signal processor elements 318 and to execute a pipeline processing for each block unit.
  • a processing is executed for each block unit, if a feedback data such as coded previous frame data are to be referred to, feedback data are input to the common memory 303 connected to the common bus 305 and memorized.
  • the process of a new video frame is performed by such processing that the other signal processor 318 than the one which data have written through common bus 305 refers the common memory 303. If the writing of the feedback data of the previous frame is not completed in the proper position in the common memory 303, the execution time of the process shall be specified.
  • each signal processor element 318 When the processing of a unit (block processing) is finished, each signal processor element 318 memorizes the status showing the completion of the present processing in the task table 304, and wait the next processing.
  • the data flow control section 301 scans the task table 304 and when the processing of the former stage signal processor element 318 is completed, it sends out an interruption signal to said signal processor element 318 and start the next processing. By repeating the operation, the execution of the operation control of each signal processor element 318 is performed.
  • each processor module 320 To conduct parallel processing in a block unit for each processor module 320, the data processing condition in the input frame buffer 313 of each processor module 320 is detected with the status information of the initial stage signal processor 318 and individual block data are distributed by proper load distribution and input to each multi-processor module 320.
  • the output control section 308 takes charge for example of a video multiplex section 257 and a transmitting buffer 258 shown in Fig. 5, and it outputs a feedback signal 269 from the transmitting buffer 258 to a coding control section 270 which takes charge of the data flow control section shown in Fig. 15.
  • the data flow control section 301 takes charge of the functions of above-mentioned load distribution and the coding control section 270 as shown in Fig. 5, and finds the block identification control signal 273 and coding control signal 274 and multiplex them in the control parameter data for the execution of the whole characteristic control.
  • Fig. 16 the processing of a single signal processor element 318 is started by the interruption from the data flow control section 301, and the contents of the parameter memory 312 is input to it through an internal bus 344.
  • the processing of one unit of block data is performed by a digital signal processor 340.
  • the result and rewritten parameters are written in a dual port memory 349, and the status is set in the task table 304 through an external bus control section 334; thus the preparation for the next process is ready.
  • An interruption control section 345 interfaces the interruption from the data flow control section 301 with the digital signal processor 340.
  • the parameter and the data written in the dual port memory 349 are read by an adjacent signal processor element 318 which is connected to a terminal 333, and the next stage process is given.
  • Fig. 18 shows the rewriting of the contents of control parameter data 302, which are added corresponding to an input block data 363, and the flow of these processes.
  • a block address which shows for example the position in a frame or time sequential order of a block, and a flag 362 which is referred to on the kind of the next process and the contents of the next process are contained in the control parameter data 302.
  • the block address 360 is used for the discrimination of a special process in a certain case for example with an end point in a picture or for the restructure of data in the output control section 308 when a process is finished.
  • the flag 362 shows for example the results etc. of coding control information 271, a block identification control signal 273, coding control signal 274, and a block identifier 253 as shown in Fig.
  • top addresses of three series of input data and of an output result storing memory are initially set by address generators 420, 421 and 422. After that the address generators are assumed to take simple increment actions.
  • a selector 434 selects the side of a register 430 and a selector 431 selects the side of a register 435.
  • the operation (ai ⁇ bi) is performed with an operator 438, and the result is stored in a register 439. This value is output from the register 439 in the next step.
  • the value of (ai ⁇ bi) can be obtained through the procedure as shown in the following: the selector 434 selects the side of the register 430 and the selector 435 selects the side of the register 431 and after the operation is executed by the operator 438 the side of the register 439 is selected by the selector 442 in the next step.
  • the value of (ai x bi) can be obtained through the procedure as shown in the following: the selector 436 selects the side of the register 430 and the selector 437 selects the side of the register 431, and after the execution of the operation with the multiplier 440 the selector 442 selects the side of the register 441 in the next step.
  • the processing speed in the case of three input one output is (2N + 10/N + 7) times of that of prior art, that is almost half times if N is a large number.
  • distortion quantity of all the pixels in the block Before the operation process, on the first block among M pieces of candidate blocks for search in the previous frame data, distortion quantity of all the pixels in the block shall be measured; the distortion quantity in this case is defined to be the minimum distortion.
  • the distortion quantity differential absolute value sum is adopted. In the distortion quantity operation about on and after the second block the calculation of differential absolute values of all pixels is not needed, but at an intermediate check point if the intermediate distortion quantity exceeds a certain value, it is judged that the ultimate distortion quantity of the block cannot be smaller than the minimum distortion D and the distortion quantity operation for the residual part is stopped.
  • the same result is obtained as that obtained with the conventional method in which the whole pixels are used for a distortion operation.
  • the distortion quantity di in this case, is smaller than the minimum distortion D
  • the value of the minimum distortion D is renewed for di
  • the motion vector index is renewed for the index i.
  • the final minimum value of distortion D and the vector index I which shows the movement to give D can be obtained by repeating such operating processes as mentioned above by the number of times corresponding to the number of searching vectors till the process proceeds up to the Mth block.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Vision & Pattern Recognition (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)
  • Image Processing (AREA)
  • Complex Calculations (AREA)
  • Image Analysis (AREA)
  • Color Television Systems (AREA)
  • Ultra Sonic Daignosis Equipment (AREA)
EP19890102717 1988-02-19 1989-02-17 Digitale Signalverarbeitungsvorrichtung Withdrawn EP0329151A3 (de)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP95114932A EP0690376B1 (de) 1988-02-19 1989-02-17 Digitalsignalverarbeitungsverfahren
EP95114933A EP0703533B1 (de) 1988-02-19 1989-02-17 Digitalsignalverarbeitungsanlage
EP95114934A EP0690377B1 (de) 1988-02-19 1989-02-17 Digitalsignalverarbeitungseinheit

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
JP63037921A JPH01211162A (ja) 1988-02-19 1988-02-19 実時間マルチプロセッサ型信号処理装置
JP37921/88 1988-02-19
JP63695/88 1988-03-18
JP63063695A JPH01237838A (ja) 1988-03-18 1988-03-18 ディジタル信号処理方式
JP298723/88 1988-11-26
JP63298722A JPH02145079A (ja) 1988-11-26 1988-11-26 動き補償演算方法
JP63298723A JPH02145077A (ja) 1988-11-26 1988-11-26 情報符号化装置
JP298722/88 1988-11-26

Related Child Applications (6)

Application Number Title Priority Date Filing Date
EP95114932.7 Division-Into 1989-02-17
EP95114933A Division EP0703533B1 (de) 1988-02-19 1989-02-17 Digitalsignalverarbeitungsanlage
EP95114933.5 Division-Into 1989-02-17
EP95114932A Division EP0690376B1 (de) 1988-02-19 1989-02-17 Digitalsignalverarbeitungsverfahren
EP95114934.3 Division-Into 1989-02-17
EP95114934A Division EP0690377B1 (de) 1988-02-19 1989-02-17 Digitalsignalverarbeitungseinheit

Publications (2)

Publication Number Publication Date
EP0329151A2 true EP0329151A2 (de) 1989-08-23
EP0329151A3 EP0329151A3 (de) 1993-02-24

Family

ID=27460495

Family Applications (3)

Application Number Title Priority Date Filing Date
EP19890102717 Withdrawn EP0329151A3 (de) 1988-02-19 1989-02-17 Digitale Signalverarbeitungsvorrichtung
EP95114932A Expired - Lifetime EP0690376B1 (de) 1988-02-19 1989-02-17 Digitalsignalverarbeitungsverfahren
EP95114933A Expired - Lifetime EP0703533B1 (de) 1988-02-19 1989-02-17 Digitalsignalverarbeitungsanlage

Family Applications After (2)

Application Number Title Priority Date Filing Date
EP95114932A Expired - Lifetime EP0690376B1 (de) 1988-02-19 1989-02-17 Digitalsignalverarbeitungsverfahren
EP95114933A Expired - Lifetime EP0703533B1 (de) 1988-02-19 1989-02-17 Digitalsignalverarbeitungsanlage

Country Status (5)

Country Link
US (1) US5155852A (de)
EP (3) EP0329151A3 (de)
KR (1) KR920006283B1 (de)
CA (1) CA1317680C (de)
DE (3) DE68929113T2 (de)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0554586A3 (en) * 1991-12-23 1993-12-01 Philips Nv Recursive video signal processor
EP0571969A3 (de) * 1992-05-26 1995-05-17 Dainippon Screen Mfg Bilddatenprozessor und Verfahren zur Verarbeitung von Bilddaten.
EP0682308A1 (de) * 1994-05-09 1995-11-15 Samsung Electronics Co., Ltd. Digitale Operationseinheit
EP0562713A3 (en) * 1992-03-24 1996-02-28 Sony Corp America Controlling signal timing in digital signal processing system
WO2001057664A3 (en) * 2000-02-04 2002-03-07 Realchip Inc Real time dsp load management system
EP1229445A1 (de) * 2001-02-02 2002-08-07 Cluster Labs GmbH Verfahren zum Betreiben eines Rechnersystems und Vorrichtung
US7016412B1 (en) 2000-08-29 2006-03-21 Koninklijke Philips Electronics N.V. System and method for dynamic adaptive decoding of scalable video to balance CPU load

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0843254A3 (de) * 1990-01-18 1999-08-18 National Semiconductor Corporation Integrierte, digital arbeitende Signalverarbeitungsanlage/Universalprozessor mit anteilig genutzten internem Speicher
US5475770A (en) * 1990-09-24 1995-12-12 Cgk Computer Gesellschaft Konstanz Mbh Parallel recognition of document images with a time-elapsed processing abortion to improve overall throughput
JP2906792B2 (ja) * 1991-11-15 1999-06-21 日本電気株式会社 ディジタルプロセッサ及びその制御方法
US6965644B2 (en) * 1992-02-19 2005-11-15 8×8, Inc. Programmable architecture and methods for motion estimation
US5499375A (en) * 1993-06-03 1996-03-12 Texas Instruments Incorporated Feedback register configuration for a synchronous vector processor employing delayed and non-delayed algorithms
JP3482660B2 (ja) * 1993-09-08 2003-12-22 ソニー株式会社 画像データ処理装置および画像データ処理方法
US5590350A (en) * 1993-11-30 1996-12-31 Texas Instruments Incorporated Three input arithmetic logic unit with mask generator
JPH0954761A (ja) * 1995-08-15 1997-02-25 Sony Corp デイジタル信号処理装置及び情報処理システム
JP3729540B2 (ja) * 1995-09-08 2005-12-21 株式会社ルネサステクノロジ 画像処理装置
US5987181A (en) * 1995-10-12 1999-11-16 Sharp Kabushiki Kaisha Coding and decoding apparatus which transmits and receives tool information for constructing decoding scheme
DE19625569A1 (de) * 1996-06-26 1998-01-02 Philips Patentverwaltung Signalprozessor
US5920353A (en) * 1996-12-03 1999-07-06 St Microelectronics, Inc. Multi-standard decompression and/or compression device
DE19703251A1 (de) * 1997-01-29 1998-11-05 Kuhn Peter Dipl Ing Eine flexible VLSI Architektur für Blockmatching mit variabler Blockgröße, für Teilblockkombinationen, beliebig berandete Objekte und Luminanzkorrektur
US5911082A (en) * 1997-02-25 1999-06-08 Audio Digitalimaging Inc. Parallel processing building block chip
US6047081A (en) * 1997-10-24 2000-04-04 Imation Corp. Image processing software system having configurable communication pipelines
JP2000020424A (ja) * 1998-06-26 2000-01-21 Class Technology:Kk アプリケーション間通信システム、アプリケーション間通信方法、及びアプリケーション間通信方法を記録したコンピュータ読み取り可能な記録媒体
US6349378B1 (en) * 1999-03-31 2002-02-19 U.S. Philips Corporation Data processing using various data processors
US6912576B1 (en) 2000-05-04 2005-06-28 Broadcom Corporation System and method of processing data flow in multi-channel, multi-service environment by dynamically allocating a socket
US20020165947A1 (en) 2000-09-25 2002-11-07 Crossbeam Systems, Inc. Network application apparatus
US20070192863A1 (en) 2005-07-01 2007-08-16 Harsh Kapoor Systems and methods for processing data flows
US8010469B2 (en) 2000-09-25 2011-08-30 Crossbeam Systems, Inc. Systems and methods for processing data flows
US9800608B2 (en) 2000-09-25 2017-10-24 Symantec Corporation Processing data flows with a data flow processor
US9525696B2 (en) 2000-09-25 2016-12-20 Blue Coat Systems, Inc. Systems and methods for processing data flows
JP3709553B2 (ja) * 2000-12-19 2005-10-26 インターナショナル・ビジネス・マシーンズ・コーポレーション 演算回路および演算方法
JP2004186978A (ja) * 2002-12-03 2004-07-02 Sanyo Electric Co Ltd データ書込方法、装置およびデジタルカメラ
WO2005043919A1 (en) * 2003-10-30 2005-05-12 Nec Electronics Corporation Image decoding apparatus and image decoding method
DE102005020808B3 (de) * 2005-05-04 2006-07-20 Micronas Gmbh Nichtflüchtige Speichereinrichtung mit einer Programmier- und Löschkontrolle
US7979368B2 (en) 2005-07-01 2011-07-12 Crossbeam Systems, Inc. Systems and methods for processing data flows
US20080181210A1 (en) * 2007-01-31 2008-07-31 Finisar Corporation Processing register values in multi-process chip architectures
US8069385B1 (en) * 2008-07-14 2011-11-29 T-Ram Semiconductor, Inc. Programmable built-in self-test architecture
WO2010086907A1 (ja) * 2009-02-02 2010-08-05 富士通株式会社 パケットキャプチャシステム、パケットキャプチャ方法、情報処理装置およびプログラム

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4169289A (en) * 1977-07-08 1979-09-25 Bell Telephone Laboratories, Incorporated Data processor with improved cyclic data buffer apparatus
US4202035A (en) * 1977-11-25 1980-05-06 Mcdonnell Douglas Corporation Modulo addressing apparatus for use in a microprocessor
JPS55105763A (en) * 1979-02-05 1980-08-13 Fanuc Ltd Address instruction system
US4484346A (en) * 1980-08-15 1984-11-20 Sternberg Stanley R Neighborhood transformation logic circuitry for an image analyzer system
US4363104A (en) * 1980-09-22 1982-12-07 Hughes Aircraft Company Imaging system having multiple image copying and hierarchical busing
US4528625A (en) * 1982-02-11 1985-07-09 Texas Instruments Incorporated Input/output instruction execution in microcomputer
US4484349A (en) * 1982-03-11 1984-11-20 Environmental Research Institute Of Michigan Parallel pipeline image processor
JPS5922165A (ja) * 1982-07-28 1984-02-04 Nippon Telegr & Teleph Corp <Ntt> アドレス制御回路
US4531200A (en) * 1982-12-02 1985-07-23 International Business Machines Corporation Indexed-indirect addressing using prefix codes
NL8304442A (nl) * 1983-12-27 1985-07-16 Koninkl Philips Electronics Nv Geintegreerde en programmeerbare processor voor woordsgewijze digitale signaalbewerking.
GB8407764D0 (en) * 1984-03-26 1984-05-02 Indep Broadcasting Authority Local movement detector
EP0169709B1 (de) * 1984-07-20 1990-06-13 Nec Corporation Realzeitverarbeitungssystem für Videosignale
CA1287161C (en) * 1984-09-17 1991-07-30 Akihiro Furukawa Apparatus for discriminating a moving region and a stationary region in a video signal
US4661849A (en) * 1985-06-03 1987-04-28 Pictel Corporation Method and apparatus for providing motion estimation signals for communicating image sequences
AU579550B2 (en) * 1985-06-10 1988-11-24 Nec Corporation Movement compensation predictive encoder for a moving picture signal with a reduced amount of information
JP2638774B2 (ja) * 1986-01-08 1997-08-06 ソニー株式会社 テレビジヨン受像機
US4709344A (en) * 1985-10-02 1987-11-24 Motorola, Inc. Programmable multifrequency digital tone receiver
US4935867A (en) * 1986-03-04 1990-06-19 Advanced Micro Devices, Inc. Signal processor memory management unit with indirect addressing using selectable offsets and modulo values for indexed address calculations
DE3851655T2 (de) * 1987-06-09 1995-02-09 Sony Corp Verarbeitung des Bewegungsvektors in Fernsehbildern.
JP2521183Y2 (ja) * 1987-09-29 1996-12-25 ソニー株式会社 ディジタル信号処理回路

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0554586A3 (en) * 1991-12-23 1993-12-01 Philips Nv Recursive video signal processor
EP0562713A3 (en) * 1992-03-24 1996-02-28 Sony Corp America Controlling signal timing in digital signal processing system
EP0571969A3 (de) * 1992-05-26 1995-05-17 Dainippon Screen Mfg Bilddatenprozessor und Verfahren zur Verarbeitung von Bilddaten.
US5448655A (en) * 1992-05-26 1995-09-05 Dainippon Screen Mfg. Co., Ltd. Image data processor and image data processing method
EP0682308A1 (de) * 1994-05-09 1995-11-15 Samsung Electronics Co., Ltd. Digitale Operationseinheit
WO2001057664A3 (en) * 2000-02-04 2002-03-07 Realchip Inc Real time dsp load management system
US6925641B1 (en) 2000-02-04 2005-08-02 Xronix Communications, Inc. Real time DSP load management system
US7016412B1 (en) 2000-08-29 2006-03-21 Koninklijke Philips Electronics N.V. System and method for dynamic adaptive decoding of scalable video to balance CPU load
EP1229445A1 (de) * 2001-02-02 2002-08-07 Cluster Labs GmbH Verfahren zum Betreiben eines Rechnersystems und Vorrichtung

Also Published As

Publication number Publication date
CA1317680C (en) 1993-05-11
DE68929100D1 (de) 1999-12-16
EP0329151A3 (de) 1993-02-24
DE68929100T2 (de) 2000-07-13
US5155852A (en) 1992-10-13
KR890013558A (ko) 1989-09-23
DE68929101T2 (de) 2000-07-13
EP0703533A1 (de) 1996-03-27
EP0690376B1 (de) 1999-11-10
EP0690376A3 (de) 1996-01-17
DE68929113D1 (de) 2000-01-13
EP0690376A2 (de) 1996-01-03
EP0703533B1 (de) 1999-11-17
DE68929113T2 (de) 2000-11-09
DE68929101D1 (de) 1999-12-23
KR920006283B1 (ko) 1992-08-03

Similar Documents

Publication Publication Date Title
EP0329151A2 (de) Digitale Signalverarbeitungsvorrichtung
EP0644492B1 (de) Gerät zur adaptiven vidio-signalverarbeitung.
US5537601A (en) Programmable digital signal processor for performing a plurality of signal processings
EP0919099B1 (de) Schaltung zur bewegungsschätzung in codierern für digitalisierte videosequenzen
KR100273629B1 (ko) 이동 벡터 평가 방법 및 장치
US5687097A (en) Method and apparatus for efficiently determining a frame motion vector in a video encoder
US6263112B1 (en) Motion vector searching apparatus and motion picture coding apparatus
US6687299B2 (en) Motion estimation method and apparatus for interrupting computation which is determined not to provide solution
US6470050B1 (en) Image coding apparatus and its motion vector detection method
EP0577102A2 (de) Adresserzeugungsschaltung zur Bildverarbeitung und Verfahren hierzu
EP0690377A2 (de) Digitalsignalverarbeitungseinheit
CA1324678C (en) Digital signal processing apparatus
US6990149B2 (en) Circuit and method for full search block matching
Assayad et al. Modelling, analysis and parallel implementation of an on-line video encoder
JPH0879761A (ja) 動き予測装置および動きベクトルを計算する装置
JP2960328B2 (ja) シストリックアーキテクチャ内に配置される「ｎ＋１」個の演算子にオペランドを供給するための装置
Pei et al. STARS: Spatial temporal graph convolution network for action recognition system on FPGAs
KR920010514B1 (ko) 디지탈 신호처리장치
Fernández et al. A high-performance architecture with a macroblock-level-pipeline for MPEG-2 coding
US5729759A (en) Data processing apparatus for performing cumulative processing on time series data
US7606996B2 (en) Array type operation device
Prayline Rajabai et al. Hardware implementation of diamond search algorithm for motion estimation
Ancona et al. Parallel architectures for vector quantization
Fleury et al. Co-design by parallel prototyping: Optical-flow detection case study
Dias et al. Fully parameterizable vlsi architecture for sub-pixel motion estimation with low memory bandwidth requirements

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): DE FR GB IT

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

AK Designated contracting states

Kind code of ref document: A3

Designated state(s): DE FR GB IT

17P Request for examination filed

Effective date: 19930819

17Q First examination report despatched

Effective date: 19950606

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION HAS BEEN WITHDRAWN

18W Application withdrawn

Withdrawal date: 19960912