EP0385694A2 - Méthode et dispositif pour la démodulation de signaux M-PSK - Google Patents

Méthode et dispositif pour la démodulation de signaux M-PSK Download PDF

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Publication number
EP0385694A2
EP0385694A2 EP90302019A EP90302019A EP0385694A2 EP 0385694 A2 EP0385694 A2 EP 0385694A2 EP 90302019 A EP90302019 A EP 90302019A EP 90302019 A EP90302019 A EP 90302019A EP 0385694 A2 EP0385694 A2 EP 0385694A2
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European Patent Office
Prior art keywords
phase
signal
phase component
delayed
produce
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
EP90302019A
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German (de)
English (en)
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EP0385694A3 (fr
Inventor
James C. Long
Michael J. Serrone
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First Pacific Networks Inc
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First Pacific Networks Inc
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Publication date
Priority claimed from US07/317,211 external-priority patent/US4881246A/en
Priority claimed from US07/317,167 external-priority patent/US4989220A/en
Application filed by First Pacific Networks Inc filed Critical First Pacific Networks Inc
Publication of EP0385694A2 publication Critical patent/EP0385694A2/fr
Publication of EP0385694A3 publication Critical patent/EP0385694A3/fr
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
    • H04L27/22—Demodulator circuits; Receiver circuits
    • H04L27/233—Demodulator circuits; Receiver circuits using non-coherent demodulation
    • H04L27/2331—Demodulator circuits; Receiver circuits using non-coherent demodulation wherein the received signal is demodulated using one or more delayed versions of itself

Definitions

  • This invention relates to digital signal processing, and more particularly, to a technique for demodulating a large class of digital phase modulated signals and to apparatus and methods for demodulating a large class of digital phase shift keyed modulated signals wherein phase change is limited to adjacent phase states.
  • PSK signals Digital phase shift keyed signals find wide application in communication.
  • the signals are produced by discrete changes in phase of a periodic waveform. Phase is changed in accordance with a serial digital data stream acting as a control signal.
  • the present invention has particular application to PSK signals wherein modulation is limited to phase transitions between adjacent phase states.
  • Prior art PSK modulation schemes have required demodulators whose complexity is proportional to the complexity of the modulated signal.
  • a binary PSK signal requires a relatively simple demodulator consisting of a single channel with a single multiplier used in connection with a local phase reference.
  • a quadrature phase shift keyed (QPSK) signal on the other hand, as in the past required two phase references and two multipliers. As the number of phase states is increased, so also is the required number of phase references, multipliers and comparators in order to distinguish between the various phase states.
  • Such circuitry is complex and potentially expensive, but in the past has been necessary to provide a sufficient margin in the signal-to-noise ratio.
  • FIG. 1 is a schematic block diagram showing a typical prior art bipolar phase shift keyed (BPSK) demodulator 10 suitable for demodulating burst mode BPSK transmissions.
  • a demodulator 10 employs a phase splitter 12 providing as two outputs a first phase component ⁇ 1 and a second phase component ⁇ 2, wherein the second phase component is provided through a short delay line 14 (providing a nominal delay of one bit period), the output of the first phase component and the second phase component being mixed together in a mixer or multiplier 16 to produce a baseband bit stream to be directed through a lowpass filter 18.
  • the output of the lowpass filter 18 is suitable for application to a two-level comparator 20, which is used to produce a stream of ones and zeroes as a digital output.
  • Quadrature phase shift keyed modulation has required more complex demodulators.
  • An example is found in the textbook Digital Communications - Satellite/Earth Station Engineering , by Kamilo Feher, (Prentice-Hall, 1983), pp. 170-171.
  • a differential offset QPSK demodulator and a differential QPSK demodulator.
  • the in-phase (I) output and the quadrature-phase (Q) output are separately converted into digital levels before recombination into a serial data stream.
  • the recombination requires a priori knowledge of the bit clock phase.
  • This demodulator only works for QPSK signals. It is believed that there have never before been such simple demodulators for higher order M-ary PSK signals.
  • a method for demodulating M-ary PSK signals wherein the modulation is limited to phase transitions between adjacent phase states which comprises generating harmonics of the modulated source signal prior to demodulation thereby to expand the phase differential between adjacent phase states, and then demodulating one of selected harmonic signals as if it were a simple two or four phase PSK signal.
  • the resultant loss of margin in the signal-to-­noise ratio is offset by corresponding simplification of the demodulation circuitry and cost savings.
  • the spectral efficiency of a complex PSK signal is retained.
  • a method and an apparatus are provided for demodulating M-ary PSK signals of the type wherein the modulation is limited to phase transitions between adjacent phase states.
  • the method is operative in a demodulator which comprises a phase splitter dividing a source signal into three paths with a preselected phase relationship among phases, one of the phases being delayed by nominally one bit period, a pair of mixers or multipliers, each one of the mixers receiving as one input a representation of the delayed-phase component and each one of the mixers receiving as a second input a representation of one of the other of the phase components.
  • Mixed signals are provided by the mixers to a combiner which adds and subtracts the combined signals according to expected input signal type to produce from one to N intermediate output signals.
  • An intermediate output signal is coupled to a corresponding two-level comparator, each of which receives and responds to the respective intermediate output signals to produce a digital output.
  • Digital logic circuitry responds to the digital outputs of each of the comparators to map the digital outputs into a single digital bit stream of ones and zeroes. The resultant loss of margin and the signal-­to-noise ratio is offset by corresponding simplification of the demodulation circuitry and cost savings. However, the spectral efficiency of a complex M-ary PSK signal is retained.
  • a method and an apparatus are provided for demodulating M-ary PSK signals of the type wherein the modulation is limited to phase transitions between adjacent phase states.
  • the method is operative in a demodulator which comprises a phase splitter dividing a source signal into only two paths with a preselected phase relationship between phases, one of the phases being delayed by nominally one bit period, a single mixer or multiplier receiving as one input a representation of the delayed-phase component and receiving as a second input a representation of the other of the phase components.
  • the output signal is coupled to at least one two-level comparator, each of which produces a digital output.
  • Digital logic circuitry responds to the digital outputs of each of the comparators to map the digital outputs into a single digital bit stream of ones and zeroes.
  • the resultant loss of margin and the signal-­to-noise ratio is offset by corresponding simplification of the demodulation circuitry and cost savings.
  • the spectral efficiency of a complex M-ary PSK signal is retained.
  • FIG. 2 there is shown a block diagram illustrating the method of converting a PSK signal in accordance with the invention.
  • An input digitally modulated signal with differential phase changes of some fraction of 360° is applied to a harmonic generator 112.
  • the harmonic generator 112 is for example, a multiplier which multiplies the input signal by itself for example, to obtain an output signal of double the frequency with phase components equal to twice the input phase such that there are half as many phase states.
  • the harmonic generator 112 may multiply by 2, 3, 4 or N times the fundamental of the input signal with the limitation at the resultant expansion in phase difference between adjacent phase states is limited to the maximum differential of up to 180°.
  • the input modulated signal from the bandpass filter 114 (Fig. 2) is applied to a phase splitter 118 which separates the input signal into two paths having equal phase ⁇ 1 and ⁇ 2.
  • the ⁇ 1 phase signals apply directly to a mixer, which is for example, a multiplier 120.
  • the second phase signal ⁇ 2 is applied to a delay line 122 whose delay is selected to be equal to the bit period of the data stream to be demodulated.
  • the output of the delay line 122 is applied to a second input of the multiplier 120 to be mixed with the input of ⁇ 1.
  • the resultant output signal is the sum and difference of the two phase signals.
  • This sum and difference signal on output line 124 is applied to a lowpass filter 126.
  • the lowpass filter 126 has a frequency character is intended to pass the difference signal only.
  • the difference signal only on line 128 is applied to a comparator 130.
  • the comparator 130 receives the analog input signal two levels and produces the desired two level digital output signal of a BPSK signal. It is understood by the processing circuitry that this BPSK signal is a representative of the input digital signal which is not in fact a BPSK signal.
  • any suitable harmonic generator may be used.
  • a non-linear element with appropriate filter could serve as a frequency multiplier, a full-wave rectifier could be employed to achieve a doubling of the resultant frequency, and any combination of the above techniques could be used for frequency harmonic generation.
  • Another potential frequency harmonic generator is a phase lock loop with a divide by N frequency divider on the output of the voltage controlled oscillator whose output is then sent back to the phase detector. This latter method is particularly advantageous in that it ideally generates only a single harmonic of the desired frequency.
  • each specific embodiment of the invention has a selected number of combiner output channels whose signals may be analyzed in combination to extract a desired digital output.
  • a first comparator 242 a second comparator 244 and digital logic circuitry 246, as hereinafter explained.
  • the phase splitter 232 has a single analog signal input 248 for receiving a modulated signal dividing a source signal into three paths with a preselected phase relationship among phases, one of the phases being delayed by nominally one bit period through the delay line 234 or its equivalent, such as a charge-coupled device (CCD).
  • CCD charge-coupled device
  • the pair of mixers 236 and 238 may be multipliers, each one of the mixers 236 and 238 receiving on one input line 250 a representation of the delayed-phase component and each one of the mixers 236 and 238 also receiving on a second input line 252 and 254 a representation of one of the other of the phase components from the phase splitter 232.
  • Examples of the phases out of the phase splitter 232 are ⁇ 1 is 0°, ⁇ 2 is 45°, and ⁇ 3 is 90°.
  • the delay of the delay line 234 is applied to the 45° phase line, and the nominal delay is one bit and the phase delay is a multiple of 360° at the carrier frequency of the input at input port 248.
  • Two combined signals on signal lines 256 and 258 are provided by the mixers 236 and 238 to the combiner 240.
  • the combiner 240 is customized to the type of demodulation desired, as hereinafter explained.
  • the combiner 240 adds or subtracts the signals with selected weighing according to expected input signal type to produce from one to N intermediate output signals on for example signal lines 260 and 262, for a two-output combination.
  • the intermediate output signals from the combiner 240 which incorporates low-pass filters, are filtered to remove extraneous high-frequency components and then are respectively coupled on signal lines 260 and 262 to corresponding two-level comparators 242 and 244, each of which responds to produce a respective digital binary-level output on output lines 264 and 266 to digital logic circuitry 246.
  • the digital logic circuitry 246 responds to the digital outputs of each of the comparators 242 and 244 to map the digital outputs into a single digital bit stream of ones and zeroes on output line 268.
  • a first example is Differential Offset Quadrature Phase Shift Keyed (DOQPSK) modulation wherein transitions are only between adjacent phase states.
  • DOQPSK Differential Offset Quadrature Phase Shift Keyed
  • the delay line 234 length is one bit with a 0° net phase shift (e.g., 720°). An error of +/- 15% on delay and net +/-15° in phase is not critical and is therefore considered to be within the meaning of one bit delay with zero net phase shift.
  • the combiner 240 comprises a first resistor 340, a second resistor 342 and a lowpass filter 344.
  • the first resistor 340 has one terminal coupled to the mixer 236 and the other terminal coupled to a mixing node 346.
  • the second resistor 342 has one terminal coupled to the mixer 238 and the other terminal coupled to the mixing node 346.
  • the mixing node 346 is coupled to the input of the lowpass filter 344.
  • the combiner 240 thus is a device having the following transfer characteristics for unity voltage at the three phase outputs of the phase splitter 232: Phase change at input Mixer One Voltage Out Mixer Two Voltage Out Combiner Volt. Out a) 0° to 90° -0.707 +0.707 0.00 b) 0° to -90° +0.707 -0.707 0.00 c) 0° to 0° +0.707 +0.707 1.414/2
  • the output of the combiner 240 is applied to a single comparator 242, since further comparators are unnecessary in the case of DOQPSK.
  • the logic level output of the comparator 242 in the above example thus for case a) is 0, for case b) is 0, and for case c) is 1.
  • a single output of the combiner 240 can be coupled to the inputs of two standard dual-input comparators 242, 244 (shown in generalization in Figure 4).
  • two standard dual-input comparators 242, 244 shown in generalization in Figure 4
  • more complex differential offset M-ary Phase Shift Keyed (DOMPSK) modulation can be analyzed with simple circuitry.
  • DOMPSK Phase Shift Keyed
  • OMPSK Offset M-ary Phase Shift Keyed
  • the combiner 240 is identical to that of the combiner of Figure 5.
  • the single output of the combiner 240 is applied on lines 260 and 262 to a positive-referenced input of a first comparator 342 and a negative-reference input of a second comparator 344, respectively, each of which is independently referenced to different voltage references of equal magnitude but opposite polarities.
  • the output of the comparators 342 and 344 in the above example thus depends on the magnitude of ⁇ to determine the binary logic levels for cases a), b), and c).
  • the logic level output of the comparator 242 in the above example thus for case a) is 1, for case b) is 1, and for case c) is 0.
  • each specific embodiment of the invention has a selected number of output channels 460, 462 from the lowpass filter 418 whose signals are coupled to two-level comparators.
  • the phase splitter 412 has a single analog signal input 448 for receiving a modulated signal dividing a source signal into only two paths with a preselected phase relationship between the two phases, usually in quadrature relationship, one of the phases being delayed by nominally one bit period through the delay line 414 or its equivalent, such as a charge-coupled device (CCD).
  • CCD charge-coupled device
  • the mixer 416 may be a multiplier receiving on one input line 450 a representation of the delayed-phase component and on a second input line 452 a representation of the other of the phase components from the phase splitter 412.
  • the delay of the delay line 414 is applied to the 90° phase line, and the nominal delay is one bit and the phase delay is a multiple of 360° at the carrier frequency of the input at input port 448.
  • a mixed signal on signal line 456 is provided by the mixer 416 to a lowpass filter 418, whereby the combined signal is filtered to remove extraneous high-­frequency components.
  • the filtered signal is then coupled on signal lines 460 and 462 to corresponding two-level comparators 442 and 444, each of which responds to produce a respective digital binary-level output on output lines 464 and 466 to digital logic circuitry 446.
  • the digital logic circuitry 446 responds to the digital outputs of each of the comparators 442 and 444 to map the digital outputs into a single digital bit stream of ones and zeroes on output line 468.
  • This demodulator works with the special case of M-ary PSK where the phase transitions are limited to adjacent phase states.
  • the circuit herein is a general case with a minimum number of circuit elements and required phase components.
  • a first example is Differential Offset Quadrature Phase Shift Keyed (DOQPSK) modulation wherein transitions are only between adjacent phase states.
  • DOQPSK Differential Offset Quadrature Phase Shift Keyed
  • the delay line 414 length is one bit with a 0° net phase shift (e.g., 720°).
  • An error of +/-15% on delay and net +/-15° in phase is not critical and is therefore considered to be within the meaning of one bit delay with zero net phase shift.
  • the following is the transfer characteristic for unity voltage at the two phase outputs of the phase splitter 412: Phase change at input 448 Mixer 416 Voltage Out Logic Level Out a) 0° to 90° 0.0 0 b) 0° to -90° 0.0 0 c) 0° to 0° 1.0 1
  • the output of the lowpass filter 418 is applied directly to a single comparator 442, since further comparators are unnecessary in the case of DOQPSK.
  • the logic level output of the comparator 442 in the above example is shown in the right-hand column of the above table. From the above, it is seen that for the case of DOQPSK, the use of a comparator to hard limit the output at a decision level of 0.5 Volt will reconstruct the original data. Digital logic circuitry 446 is unneeded to decode the output of a single comparator, such as the comparator 442. Hence, the output of the comparator 442 is the desired digital data stream.
  • a single output of the lowpass filter 418 can be coupled to the inputs of two standard dual-input comparators 442, 444 (shown in generalization in Figure 7).
  • two standard dual-input comparators 442, 444 shown in generalization in Figure 7
  • more complex differential offset M-ary Phase Shift Keyed (DOMPSK) modulation can be analyzed with simple circuitry.
  • DOMPSK Phase Shift Keyed
  • a second example is an Offset M-ary Phase Shift Keyed (OMPSK) modulation wherein transitions are only between adjacent phase states.
  • OMPSK Offset M-ary Phase Shift Keyed
  • the single output of the lowpass filter 418 is applied on lines 460 and 462 to a positive-referenced input of a first comparator 442 and a negative-reference input of a second comparator 444, respectively, each of which is independently referenced to different voltage references 461, 463 of equal magnitude but opposite polarities.
  • the output of the comparators 442 and 444 in the above example thus depends on the magnitude of ⁇ to determine the binary logic levels for cases a), b), and c). A specific example is shown above.
  • the digital logic circuitry 246 and 446 are merely two-input OR gates.
  • the digital logic circuits 246 and 446 would be of a design to provide decoding of signals from a plurality of comparators into a single digital data bit stream. In such a configuration, more complex differential and nondifferential offset M-ary Phase Shift Keyed modulation can be demodulated with simple circuitry.
  • comparing comprises identifying each phase state by means of a group of comparators 242, 244 ( Figure 4) or 442, 444 ( Figure 8), the number of individual comparators 442, 444 being one less than the number of possible phase states. It is therefore not intended that this invention be limited, except as indicated in the appended claims.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
EP19900302019 1989-02-28 1990-02-26 Méthode et dispositif pour la démodulation de signaux M-PSK Withdrawn EP0385694A3 (fr)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US31715589A 1989-02-28 1989-02-28
US317211 1989-02-28
US07/317,211 US4881246A (en) 1989-02-28 1989-02-28 Method and apparatus for demodulating a class of M-ary phase shift keyed (PSK) signals
US07/317,167 US4989220A (en) 1989-02-28 1989-02-28 Method and apparatus for demodulating a class of M-ary phase shift keyed (PSK) signals
US317155 1989-02-28
US317167 1989-02-28

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EP0385694A2 true EP0385694A2 (fr) 1990-09-05
EP0385694A3 EP0385694A3 (fr) 1992-07-01

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JP (1) JPH02284550A (fr)
KR (1) KR910016170A (fr)
CA (1) CA2009712A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1475935A3 (fr) * 2003-05-06 2007-05-16 Samsung Electronics Co., Ltd. Transmission à bande ultra-large à MDPD

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE332201B (fr) * 1969-07-02 1971-02-01 Ericsson Telefon Ab L M
US4064361A (en) * 1975-12-31 1977-12-20 Bell Telephone Laboratories, Incorporated Correlative timing recovery in digital data transmission systems
US4416016A (en) * 1981-06-11 1983-11-15 Bell Telephone Laboratories, Incorporated Differential phase shift keyed receiver

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1475935A3 (fr) * 2003-05-06 2007-05-16 Samsung Electronics Co., Ltd. Transmission à bande ultra-large à MDPD

Also Published As

Publication number Publication date
KR910016170A (ko) 1991-09-30
CA2009712A1 (fr) 1990-08-31
JPH02284550A (ja) 1990-11-21
EP0385694A3 (fr) 1992-07-01

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