EP0397780A1 - Circuit integre pourvu d'organes reduisant les dommages dus aux decharges electrostatiques - Google Patents

Circuit integre pourvu d'organes reduisant les dommages dus aux decharges electrostatiques

Info

Publication number
EP0397780A1
EP0397780A1 EP89902440A EP89902440A EP0397780A1 EP 0397780 A1 EP0397780 A1 EP 0397780A1 EP 89902440 A EP89902440 A EP 89902440A EP 89902440 A EP89902440 A EP 89902440A EP 0397780 A1 EP0397780 A1 EP 0397780A1
Authority
EP
European Patent Office
Prior art keywords
dielectric
layer
substrate
temperature
junction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP89902440A
Other languages
German (de)
English (en)
Other versions
EP0397780A4 (en
Inventor
Jerome F. Lapham
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Analog Devices Inc
Original Assignee
Analog Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Analog Devices Inc filed Critical Analog Devices Inc
Publication of EP0397780A1 publication Critical patent/EP0397780A1/fr
Publication of EP0397780A4 publication Critical patent/EP0397780A4/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/60—Arrangements for protection of devices protecting against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]

Definitions

  • This invention relates to integrated circuits (ICs) comprising a substrate carrying a large number of circuit elements such as transistors and the like. More particularly, this invention relates to ICs having means to reduce damage from the effects of electrostatic dis ⁇ charge (ESD) .
  • ESD electrostatic dis ⁇ charge
  • Electrostatic Dis ⁇ charge (ESD) events It is well known that ICs are subject to serious damage or destruction as a result of Electrostatic Dis ⁇ charge (ESD) events.
  • the electrostatic voltage associated with the discharge can be developed by any of many sources, such as lightning, or friction between insulating bodies such as synthetic fiber clothing. Damage occurs when the ESD voltage is accidentally coupled to one of the circuit terminals and thence to some portion of the metal inter ⁇ connect layer of the IC.
  • the metal interconnect is typically an Aluminum layer laid down over an oxide coating overlying the top surface of the semiconductor.
  • the ESD voltage can cause a current to flow from the metal through the normally nonconducting oxide coating to the underlying semi ⁇ conductor. The current then leaves the IC through some other circuit terminal. The magnitude of the current is often sufficient to cause significant dam ⁇ age to the oxide, particularly by leaving it permanently conducting. The resulting shunt path often causes circuit failure.
  • ICs are made with semiconductive elements which, unlike MOS transistors, do not require thin oxides, for example bipolar transistors. These ICs nevertheless may as a result of the particular process steps carried out have thin oxides in certain places, or may have had the usual thermal oxide completely or almost completely removed in selected places, and are thus susceptible to ESD induced damage. This inven ⁇ tion describes a process for use with such ICs which eliminates the need to provide specific protection devices in accordance with prior practice.
  • a critical characteristic in accordance with the invention is that the total thickness of the insula- tive coating between the substrate and the metal intercon ⁇ nect is made great enough to assure that the dielectric breakdown voltage through the insulation is greater than the breakdown voltage of any of the junctions formed in the substrate.
  • the breakdown occurs at a junction, not through the insulative coating. Since junction damage is self-healing, the injury to the IC will not be permanent as it would be if the breakdown occurred in the insulative coating.
  • a second critical characteristic in accordance with the invention is that the thick insulative coating on the substrate is at least partly comprised of low- temperature (LT) dielectric material deposited after formation of the junctions. Deposition at relatively low temperatures assures that no detrimental changes occur in the already-formed junctions.
  • LT low- temperature
  • an IC structure wherein the insulative coating for the sub ⁇ strate comprises two adjacent layers just beneath the metal interconnect.
  • the first layer of the coating is the usual thermally-grown Silicon dioxide, formed at a relatively high temperature during conventional process ⁇ ing of the integrated circuit.
  • the second layer is a deposited layer of Silicon dioxide, developed at a rela ⁇ tively low temperature, sufficiently low to assure that already-formed junctions in the IC are not altered detri ⁇ mentally during deposition of the oxide.
  • the thermally-grown oxide laid down during conventional IC processing may be partially or wholly removed, at least in selected regions of the substrate, prior to deposition of a low-temperature insulative coating of thickness suf ⁇ ficient to minimize the possibility of ESD damage in accordance with the invention.
  • FIGURE 1 is a vertical section through an inte ⁇ grated circuit chip, not to scale and with certain aspects shown pictorially;
  • FIGURE 2 is a schematic diagram representing elements of the IC chip of Figure 1;
  • FIGURE 3 is a graphical presentation to aid in explaining the operation of the invention.
  • an integrated circuit comprising a substrate 10, commonly made of Silicon and shown in this example as being p-type.
  • This substrate is supplied with n-type impurities by conven ⁇ tional techniques, such as chemical vapor deposition (CVD) or ion implantation. These impurities are driven-in (diffused) into the substrate so as to form an n-type region 12 estab ⁇ lishing a junction 14 with the p-type substrate material.
  • a diode symbol 16 is shown at the junction to illustrate pic ⁇ torially the electrical characteristics of the junction.
  • a typical IC will of course include a multiplic ⁇ ity of other junctions (not shown) , forming both diodes and transistors which together comprise the elements of the cir ⁇ cuit of the particular IC device. These other junctions are not shown herein in order to simplify the presentation.
  • a protective insulating di ⁇ electric layer such as Silicon dioxide, illustrated at 20, is thermally grown over the surface of the substrate, in known fashion.
  • This layer is formed at a relatively high temperature, preferably above 700°C.
  • 0 2 oxygen
  • H_0 water vapor
  • Si ⁇ 2 Silicon dioxide
  • portions of the ther ⁇ mally-grown oxide must be removed in various places, as part of the implant and/or diffusion processes involved in making the many IC junctions, the final thickness of this oxide layer 20 will vary considerably from place to place, as shown in Figure 1.
  • a layer of metallization such as illustrated at 22 normally is laid down next, over the thermally-grown oxide 20, in order to make electrical connections to selected regions of the sub ⁇ strate surface.
  • ESD electrostatic discharge
  • Such ESD voltage is diagrammatic- ally illustrated in Figure 1 by a symbolic voltage source 24 with one terminal poised to be connected to the metalli ⁇ zation layer 22, and its other terminal connected to ground. It has been found that the excessive sensitivity to ESD in the prior art IC constructions can be overcome or substantially mitigated by a new IC construction, and process of making such an IC, as will now be described.
  • an additional layer 26 of oxide is laid down, in this case over the thermally-grown layer 20, just beneath the metallization layer 22.
  • This addi ⁇ tional layer is formed at a relatively low temperature (below 700°C) .
  • This distinction is important, because the addition of a low- temperature (LT) oxide assures that creation of the layer does not adversely affect the junctions which already have been formed in the substrate.
  • the additional layer 26 is made sufficiently thick so as to assure that the total thickness of the oxide coating (20, 26) is sufficient that the dielectric break ⁇ down voltage (V-- TM ..) of the dielectric material between the substrate and metallization layer 22 is greater than the junction breakdown voltage ( v ⁇ BKr of the IC, in this case, the breakdown voltage of the junction 14.
  • Figure 2 illustrates how the ESD source 24 is in effect connected to the paralleled combination of the minimum breakdown- voltage dielectric region (i.e., where the dielectric is thinnest, and shown as a capacitor 30) and the minimum breakdown-voltage junction (diode 16, illustratively).
  • the current in the dielectric gradually increases (the magnitude being shown exaggeratedly in Figure 3) with increases in voltage until the dielectric breakdown voltage is reached. At that point, the current increases rapidly, and the voltage decreases to a very low level (reflecting the near short circuit represented by the dielectric material after break ⁇ down) .
  • the magnitude of the dielectric breakdown voltage V__, VT _. is increased as compared to the breakdown voltage for the thermally-grown layer (20) by itself.
  • the actual dielectric breakdown voltage is given (somewhat conservatively) by the following relationship:
  • V DBKD ( * 06 Vo l ts / A ngstroms) (thickness in Angstroms)
  • a thickness of 10,000 A thus will provide protection against an ESD event of about 600 volts. With rare exceptions, all IC junctions break down at voltages less than 600 volts.
  • the final dielectric coating (20, 26) prefer ⁇ ably is made sufficiently thick that its breakdown voltage V BKD is greater than the junction breakdown voltage V , shown as a vertical dotted line in the first quadrant of the Figure 3 graph.
  • the diode 16 will be forward-biased and will pass current at volt ⁇ ages much less than the dielectric breakdown voltage of the oxide, thus protecting the oxide in the same way.
  • the low-temperature oxide coating can be depos ⁇ ited prior to the metallization mask step in any of various ways.
  • chemical vapor deposition CVD
  • silane gas SiH.
  • Sputtering also can be employed.
  • Still other sources and oxidants can be used, e.g. tetraethyl orthosilicate and nitrous oxide.
  • the Silicon for the low temperature SiOick coating is supplied externally, i.e. it is not derived from the substrate as it is with thermally-grown (high-temperature) oxide.
  • the substrate is provided with a multilayer oxide coating, wherein one layer is a high-temperature (HT) layer next to the substrate, and the other is a low-temper ⁇ ature (LT) layer 26 just beneath the metallization layer.
  • HT high-temperature
  • LT low-temper ⁇ ature
  • the high-temperature oxide may be partially or fully removed, at least in some places, prior to deposit of the low-temper ⁇ ature (LT) insulative coating, in which event the LT coat ⁇ ing thickness must be made sufficient by itself to assure the necessary dielectric breakdown voltage.
  • LT low-temper ⁇ ature

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

La puce de circuit intégré décrite, qui est pourvue d'organes empêchant ou réduisant les dommages dus aux décharges électrostatiques, utilise un revêtement diélectrique épais (20, 26) en oxyde isolant placé entre la surface du substrat de la puce et le film de métallisation (22) utilisé pour établir un contact avec des régions du substrat (10). Au moins une partie de cette couche (26) est formée à des températures inférieures à 700°C. Le revêtement (20, 26) est suffisamment épais partout, de sorte que sa tension de rupture est supérieure à la tension de rupture de n'importe quelle jonction (14) présente dans le substrat (10), ce qui est une assurance que les ruptures causées par des décharges électrostatiques se produisent toujours dans la jonction (14), qui se répare d'elle même, plutôt que dans le revêtement diélectrique (20, 26), où le dommage pourrait être permanent.
EP19890902440 1988-02-02 1989-01-23 Ic with means for reducing esd damage Withdrawn EP0397780A4 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15155588A 1988-02-02 1988-02-02
US151555 1993-11-12

Publications (2)

Publication Number Publication Date
EP0397780A1 true EP0397780A1 (fr) 1990-11-22
EP0397780A4 EP0397780A4 (en) 1991-09-18

Family

ID=22539291

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19890902440 Withdrawn EP0397780A4 (en) 1988-02-02 1989-01-23 Ic with means for reducing esd damage

Country Status (4)

Country Link
EP (1) EP0397780A4 (fr)
JP (1) JPH03502389A (fr)
CA (1) CA1303753C (fr)
WO (1) WO1989007334A1 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2268328B (en) * 1992-06-30 1995-09-06 Texas Instruments Ltd A capacitor with electrostatic discharge protection
GB9907910D0 (en) * 1999-04-07 1999-06-02 Koninkl Philips Electronics Nv Thin film capacitor element
CN100583437C (zh) * 2005-03-02 2010-01-20 Nxp股份有限公司 电子器件及其使用
JP5633663B1 (ja) * 2013-01-23 2014-12-03 株式会社村田製作所 薄膜キャパシタとツエナーダイオードの複合電子部品およびその製造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5587444A (en) * 1978-12-26 1980-07-02 Fujitsu Ltd Method of forming insulating film on semiconductor surface
NL8100347A (nl) * 1981-01-26 1982-08-16 Philips Nv Halfgeleiderinrichting met een beveiligingsinrichting.
EP0218685B1 (fr) * 1985-04-08 1993-03-17 STMicroelectronics, Inc. Circuit d'entree protege contre les decharges electrostatiques
US4763184A (en) * 1985-04-30 1988-08-09 Waferscale Integration, Inc. Input circuit for protecting against damage caused by electrostatic discharge
US4806999A (en) * 1985-09-30 1989-02-21 American Telephone And Telegraph Company, At&T Bell Laboratories Area efficient input protection
US4736271A (en) * 1987-06-23 1988-04-05 Signetics Corporation Protection device utilizing one or more subsurface diodes and associated method of manufacture

Also Published As

Publication number Publication date
WO1989007334A1 (fr) 1989-08-10
JPH03502389A (ja) 1991-05-30
CA1303753C (fr) 1992-06-16
EP0397780A4 (en) 1991-09-18

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