EP0446893A1 - Verfahren zur Herstellung von Halbleiterbauelementen mit Floatinggates - Google Patents

Verfahren zur Herstellung von Halbleiterbauelementen mit Floatinggates Download PDF

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Publication number
EP0446893A1
EP0446893A1 EP91103833A EP91103833A EP0446893A1 EP 0446893 A1 EP0446893 A1 EP 0446893A1 EP 91103833 A EP91103833 A EP 91103833A EP 91103833 A EP91103833 A EP 91103833A EP 0446893 A1 EP0446893 A1 EP 0446893A1
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EP
European Patent Office
Prior art keywords
region
substrate
ion
gate electrode
manufacturing
Prior art date
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Granted
Application number
EP91103833A
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English (en)
French (fr)
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EP0446893B1 (de
Inventor
Eiji C/O Intellectual Property Division Sakagami
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Toshiba Corp
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Toshiba Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0411—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having floating gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs
    • H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
    • H10D62/299—Channel regions of field-effect devices of FETs of IGFETs having lateral doping variations
    • H10D62/307—Channel regions of field-effect devices of FETs of IGFETs having lateral doping variations the doping variations being parallel to the channel lengths
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/222—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Definitions

  • the present invention relates to a method of manufacturing a semiconductor device. More particularly, the invention is applicable to the formation of a floating-gate type memory cell in the manufacture of a non-volatile semiconductor memory.
  • Fig. 1 designates a conventional non-volatile memory presented for explaining the DSA structure.
  • the reference numeral 11 designates a P-type silicon substrate, 12 oxidized film for separation, 13a a source region containing N+ type impurities, 13b a drain region containing N+ type impurities, 14 a floating gate, 15 a control gate, 16 a region containing P type impurities, 17 a channel region, 18 a gate insulation film, and 19 designates an insulation film between gate electrodes, respectively.
  • the region 16 containing P type impurities having density stronger than that is present in the center of the channel region 17 is provided by way of surround the drain region 13b of an N-channel type cell transistor.
  • the region 16 is hereinafter merely called the "P-pocket" region.
  • profile of the density of impurities in the P-pocket region 16 adjacent to an edge of the drain region 13b of the floating gate is particularly important.
  • the density of impurities in the P-pocket region 16 close to an edge of the drain region 13b must constantly be held stronger than that is present in the channel region 17. Nevertheless, since the P-pocket region 16 is formed by means of P-type impurities aides by injection of ion after completing the formation of stratified gate electrodes, it results in the occurrence of problem described below.
  • the edge of the drain 13b is covered with stacked gate electrodes.
  • a conventional ion injection method in order to prevent occurrence of "channeling effect", in other words, in order to prevent ion from deeply being injected beyond path which allows easy passage of ion, only a maximum of 7 degrees of angle is applied to the injection of ion against the normal of the silicon substrate 11, and thus, the P-type impurities cannot fully be injected into the region close to the drain region 13b below the floating gate 14.
  • any conventional art injects ion needed for the formation of the P-pocket region 16, and then executes an annealing process to diffuse the P-type impurities into such region father than the edge of the drain region 13b below the channel region 17 before eventually injecting ion needed for the formation of the source and drain regions 13a and 13b.
  • an additional round of annealing process is needed for the formation of the P-pocket region 16 containing the DSA structure.
  • the junction breakdown voltage is determined by the breakdown voltage of a high P-type impurity region formed of the overlapping portions the P-pocket region and a channel stopper region located below an isolation region, and by the breakdown voltage of the pn junction formed between the N+ regions of the regions 13a and 13b. Because of this, the junction breakdown voltage is largely dependent on the distribution of the density of impurities present in those adjacent regions.
  • the object of the invention is to provide a novel method of manufacturing a semiconductor device which promotes own capability of controlling profile of the density of P-type impurities in the drain or source regions adjoining the channel region of a stacked gate type non-volatile memory cell so that own performance capability can be promoted furthermore.
  • the invention provides a novel method of manufacturing a semiconductor device comprising those sequential steps including the following; forming a floating gate electrode on an insulation film formed on a layer, said floating gate electrode located above that region of the layer in which a first conductivity type channel is to be formed, and forming a control gate on another insulation film formed on the floating gate electrode; and injecting ions of an impurity having a first conductivity type into a semiconductor substrate at an angle of at least 8° to the normal to the substrate, thereby to form a region having a high concentration of the first conductivity type impurity, in the vicinity of a boundary a diffusion layer which contains an impurity of a second conductivity type and which is to form a drain region of a transistor having said control gate electrode.
  • the method embodied by the invention characteristically executes those sequential steps including the following;
  • the system embodied by the invention continuously or intermittently rotates the semiconductor substrate while injecting impurities into superimposed gate electrode layers in conjunction with ion for the formation of a P-pocket region; next, the system injects ion into lateral surface of the superimposed gate electrode layers by applying a minimum of 8 degrees of angle in order to promote the density of impurities in the P-pocket region adjacent to the edge of the drain region below the floating gate electrode.
  • the system embodied by the invention can securely vary voltage available for accelerating the ion injection speed and also vary the angle for injecting ion into the semiconductor substrate as well. Based on those techniques mentioned above, the system embodied by the invention simultaneously controls the profile of the density of impurities in the ion-injected region and the "short-channel" effect from occurrence, thus effectively promoting the data writing efficiency.
  • the system embodied by the invention injects ion into the semiconductor substrate by applying a minimum of 8 degrees and a maximum of 60 degrees of angle against the normal of this substrate. This is because, like any conventional art, if ion were injected into the substrate at a maximum of 7 degrees of angle against the normal of the substrate, then the effect of strengthening the density of impurities will be minimized in the P-pocket region adjacent to the edge of the drain region below the floating gate electrode. Injection of ion at a minimum of 8 degrees of angle initiates promotion of density of impurities beyond the conventionally available level. Conversely, if the ion injection angle exceeds 60 degrees, then difficulty is present in the effect of fully injecting ion into the substrate. Since the system embodied by the invention injects ion at a minimum of 8 degrees against the normal of the substrate, the above-cited channel effect arises. Nevertheless, since ion is deeply injected, no critical problem arises.
  • the system embodied by the invention forms a field insulation film 22 and a channel stopper region 23 on the surface of a P-type silicone substrate 21, then separates elements.
  • the P-type silicone substrate 21 is superficially provided with a gate insulation film 24 having about 20 nm of thickness.
  • a gate insulation film 24 having about 20 nm of thickness.
  • the art embodied by the invention forms the channel region merely by applying the P-type impurities held in the P-type silicone substrate 21 without injecting the ionized P-type impurities therein for strengthening the density.
  • the system forms phosphor-doped polycrystalline silicon layer 25 on the gate insulation film 24, where this layer 24 is available for composing a floating gate electrode.
  • thermally oxidized film 26 having about 20 nm of thickness is formed on the polycrystalline silicone layer 25 by applying a thermal oxidation process.
  • the system forms the secondary phosphor-doped polycrystalline silicon layer 27 on the thermally oxidized film 26 (see Fig. 2A), where this layer 27 is available for composing a control gate electrode.
  • the system injects the P-type impurities into the P-type silicon substrate 21 in conjunction with ion by way of self-aligned the stacked gate electrode unit serving as mask, and then forms up ion-injected P-type layers 32a and 32b adjoining those regions predetermined to become source and drain regions.
  • Ion is injected into the P-type silicon substrate 21 while continuously rotating it more than 1 round per minute by injecting more than 5 ⁇ 1012 cm ⁇ 2 of a dosed amount of boron by applying 10 ⁇ ⁇ ⁇ 45 degrees of angle against the normal 33 of the silicone substrate 21 (see Fig. 2C and 2D).
  • care be taken to inject ionized impurities by properly adjusting the density of impurities to be stronger than that is present in the center of the channel region and weaker than that is present in the drain region of this cell transistor.
  • the process of ion injection can be implemented in accordance with the method of manufacturing semiconductor device based on the condition specified by the expression shown below.
  • X p designates the mean projected range of the P-type conductive impurities injected into the P-pocket region in conjunction with ion from the surface of the P-type silicone substrate;
  • ⁇ designates the angle at which ion is injected against the normal of the P-type silicon substrate;
  • X jl designates the extended distance of the edge of the drain or source region as a result of elongation in the direction of the channel region below the stacked gate electrode unit by effect of diffusion until reaching the final production step after completing the ion injection process (see Fig. 3).
  • the density of impurities in the P-pocket region at the edge of the drain region can sufficiently be strengthened only when the product of tan ⁇ and the distance X p designating the mean projected range of the P-type impurities injected into the P-pocket region together with ion from the surface of the P-type silicone substrate is greater than the distance X jl designating the distance of the edge of the drain region diffused into the portion below the floating gate electrode. This allows the P-pocket region to fully exert own functional effect.
  • the P-type impurities were not deeply injected, then it will cause the P-type impurities to be absorbed into the superficial oxidized film generated by the following thermal treatment including oxidation, thus resulting in the ineffective application of the P-type impurities.
  • the P-pocket region is effective when the value of ⁇ is more than 28 degrees.
  • the embodiment of the invention allows the P-type impurities to effectively be injected into the P-pocket region by applying a minimum of 8 degrees and a maximum of 60 degrees as well.
  • the reference numeral 34 shown in Figs. 2C and 2D designates beam of ion containing P-type impurities.
  • the reference numeral 36a and 36b designate ionized P-type impurities injected into field edge.
  • the reference numeral 21 designates the rotating P-type silicon substrate.
  • the P-type impurities contained in ion is injected into the substrate by way of self-aligned the stacked gate electrode unit functioning as mask, and then N-type ion-injected layers 39a and 39b are respectively formed.
  • ion is injected into the P-type silicone substrate 21 so that the injection can be oriented in parallel with the lateral surface of the stacked gate electrode unit or at an angle of 7° to the normal to the surface of the silicon substrate 21.
  • 5 ⁇ 1015 cm ⁇ 2 of a dosed amount of ionized arsenic is injected into the silicon substrate 21.
  • the reference numeral 38 shown in Fig. 2E designates beam of ionized N-type impurities.
  • a thermal process such as an annealing process is executed at 900°C in order to activate ionized impurities and recover the oxidized film 24, 31 from damage incurred from the said two injections of ion.
  • the ion-injected P-type layers 32a and 32b respectively form P-pocket regions 40a and 40b.
  • the ion-injected N-type layers 32a and 32b respectively form source and drain regions 41a and 41b.
  • an insulation film 42 above the source and drain regions 41a and 41b is perforated to provide a contact hole 43.
  • an aluminium electrode 44 is formed, thus completing the production of an EPROM cell (see Fig. 2F).
  • the reference numeral 45 shown in Fig. 2F designates the portion where the P-pocket region and the channel stopper region overlap each other.
  • the reference numeral 46 designates the channel region.
  • the density of P-type impurities in the P-pocket region adjacent to the edge of the drain region can securely be strengthened, where the density of P-type impurities makes up the decisive factor of the DSA structure.
  • the efficiency of writing data into the cell memory is promoted.
  • "short-channel" effect is improved, thus easily allowing materialization of finer size of the cell and integration of densely built circuits as well.
  • Fig. 3 designates the sectional views of those regions adjacent to the drain edge of the cell embodied by the invention.
  • the P-pocket region shown in Fig. 3 with a broken line designates the case in which the conventional ion injection method is applied to the formation of the P-pocket region of the above embodiment.
  • the reference character X j shown in Fig. 3 designates the depth of the junction of the drain region 41b, whereas X jl designates the extended distance of the edge of the drain or source region as a result of elongation in the direction of the channel region below the floating gate electrode by effect of diffusion until reaching the final production process after completing the ion injection process.
  • Fig. 3 designates the sectional views of those regions adjacent to the drain edge of the cell embodied by the invention.
  • the P-pocket region shown in Fig. 3 with a broken line designates the case in which the conventional ion injection method is applied to the formation of the P-pocket region of the above embodiment.
  • FIG. 4 graphically designates concrete distribution of the density of impurities across the A-A' section shown in Fig. 3.
  • the density of boron shown by means of a broken line designates the case in which the conventional ion injection method is applied to the formation of the P-pocket region of the above embodiment.
  • the system of manufacturing the semiconductor device according to the invention provides those useful advantages described below.
  • the scope of the invention is by no means confined to the embodiment thus far described, but the invention is also applicable to a variety of uses.
  • the above embodiment has formed the P-pocket region by way of covering the source and drain regions (see Fig. 2F).
  • the P-pocket region shown in Figs. 5A and 5B can also locally be provided via a masking process by causing the P-type silicon substrate 21 to stand sill or intermittently rotate itself.
  • the description of the above embodiment has solely referred to the case of forming up the P-pocket region on both sides of the drain and source regions, it is quite apparent that the embodiment can also provide the P-pocket region solely on the part of the drain region or the source region via a masking process. Furthermore, although the above description has solely referred to the N-channel type cell transistor, the embodiment of the invention is also applicable to the P-channel type cell transistor as well.

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  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
EP91103833A 1990-03-13 1991-03-13 Verfahren zur Herstellung von Halbleiterbauelementen mit Floatinggates Expired - Lifetime EP0446893B1 (de)

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JP6153190 1990-03-13
JP61531/90 1990-03-13

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EP0446893A1 true EP0446893A1 (de) 1991-09-18
EP0446893B1 EP0446893B1 (de) 1997-05-21

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US (1) US5147811A (de)
EP (1) EP0446893B1 (de)
KR (1) KR940010930B1 (de)
DE (1) DE69126156T2 (de)

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US5444279A (en) * 1993-08-11 1995-08-22 Micron Semiconductor, Inc. Floating gate memory device having discontinuous gate oxide thickness over the channel region
EP0656663A3 (de) * 1993-12-01 1995-08-30 Nec Corp Nichtflüssige-Halbleiterspeicheranordnung und Verfahren zur Löschung und Herstellung.
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EP0696050A1 (de) * 1994-07-18 1996-02-07 STMicroelectronics S.r.l. Nicht-flüchtiger EPROM und Flash-EEPROM-Speicher und Verfahren zu seiner Herstellung
GB2301709A (en) * 1995-06-02 1996-12-11 Hyundai Electronics Ind Method of forming a junction in a flash eeprom cell
EP0731494A3 (de) * 1995-03-08 1998-05-20 Advanced Micro Devices, Inc. Herstellungsverfahren für integrierten Schaltkreis unter Benutzung von Bor-Implantat
EP0744754A3 (de) * 1995-05-25 1999-03-17 AT&T Corp. Verfahren und Vorrichtung für Injektion von heissen Ladungsträgern
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JPWO2016203545A1 (ja) 2015-06-16 2017-11-24 三菱電機株式会社 半導体装置の製造方法

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Cited By (19)

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Publication number Priority date Publication date Assignee Title
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US5147811A (en) 1992-09-15
DE69126156D1 (de) 1997-06-26
EP0446893B1 (de) 1997-05-21
DE69126156T2 (de) 1997-10-09
KR940010930B1 (ko) 1994-11-19

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