Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
  • G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
  • G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
  • G06F9/30152—Determining start or end of instruction; determining instruction length
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F9/3802—Instruction prefetching
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F9/3802—Instruction prefetching
  • G06F9/3808—Instruction prefetching for instruction reuse, e.g. trace cache, branch target cache
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F9/3802—Instruction prefetching
  • G06F9/3812—Instruction prefetching with instruction modification, e.g. store into instruction stream
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F9/3818—Decoding for concurrent execution
  • G06F9/382—Pipelined decoding, e.g. using predecoding
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units

Definitions

• halfwords which exist in an instruction are initialized to indicate that the halfword is not an initial compound instruction. Best pairs are picked for compounding according to said compounding rules.
• the system employs a technique for choosing instructions for com ⁇ pounding includes instructions which cannot be compounded and certain instructions which are examined are tagged to indicate that a specific instruc ⁇ tion is not an initial instruction, and in the event that the initial instruction of the set being examined is not an appropriate as an initial compound instruc ⁇ tion marking that instruction that it is not an initial instruction.
• the system proceeds to examine a subsequent group of instructions which includes the next sequential instruction in the group which had just been examined.
• FIGURE 14 illustrates the logical and hardware implementation of the worst case compounder.
• FIGURE 16 illustrates a compounding example of the worst case with four instructions per group.
• the tag bits which are generated in memory, are "1" for the first compounded instruction and "zero" for the second compounded instruction. However, if the first and second instructions cannot be compounded, the tag bit for the first instruction is "zero" and the second and third instructions are then considered for compounding.
• the unique technique of this invention works equally well with either fixed or variable length instructions since once the start of an instruction is known (or pre- sumed), the length can always be found in one way or another somewhere in the instructions.
• the length is encoded in the opcode, while in other systems the length maybe encoded in the operands.
• the illus ⁇ trated examples of opcodes illustrated may be either fixed or of variable length.
• This storage mechanism includes a first storage mechanism for storing instructions and data to be processed in the form of a series of base instructions for a scalar machine.
• This storage mechanism is identified as higher-level storage 136.
• This storage (also "main memory”) is a large capacity lower speed storage mech ⁇ anism and may be, for example, a large capacity system storage unit or the lower portion of a comprehensive hierarchical storage system.
• the computer system of FIGURE 4-B also includes an instruction fetch and issue mechanism coupled to compound instruction cache 138 for supplying adjacent instructions stored therein to different ones of the functional instruc ⁇ tion processing units 139-141 when the instruction tag bits indicate that they may be processed in parallel.
• This mechanism also provides single instructions to individual functional units when their tag bits indicate parallel execution is not possible and they must be processed singly.
• This mech ⁇ anism is represented by instruction fetch and issue unit 142.
• Fetch and issue unit 142 fetches instructions form the cache 138 and examines the tag bits and instruction operation code (opcode) fields, performing a decode function, and based upon such examinations sends the instruction under consideration to the appropriate ones of the functional units 138- 141. .
• the bits T of FIGURE 9 are defined to indicate a specific meaning.
• the t 0 bit will mark the beginning of an instruction, as illustrated below. In all cases a 0 shall mean not asserted. In all cases it is preferred to have the compound instruction fetched with a certainty. Accordingly, the number of bits chosen for fetching is the maximum of number of bits which may be contained and could be executed with an instruction of the maximum instruction length of the target machine which is executing the parallel com ⁇ pounded instructions. Thus the fetching system provides for maximum length fetching.

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• Engineering & Computer Science (AREA)
• Software Systems (AREA)
• Theoretical Computer Science (AREA)
• Physics & Mathematics (AREA)
• General Engineering & Computer Science (AREA)
• General Physics & Mathematics (AREA)
• Advance Control (AREA)
• Executing Machine-Instructions (AREA)
• Multi Processors (AREA)
• Devices For Executing Special Programs (AREA)

Applications Claiming Priority (8)

Publications (2)

Family

ID=46201961

Family Applications (2)

Family Applications Before (1)

Country Status (7)

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Family Cites Families (12)

• 1991
  • 1991-03-29 PL PL91293182A patent/PL166513B1/pl not_active IP Right Cessation
  • 1991-03-29 WO PCT/US1991/002037 patent/WO1991017496A1/en not_active Ceased
  • 1991-03-29 HU HU9200024A patent/HU216990B/hu unknown
  • 1991-03-29 AT AT91908085T patent/ATE194236T1/de not_active IP Right Cessation
  • 1991-03-29 JP JP3507600A patent/JPH0679273B2/ja not_active Expired - Fee Related
  • 1991-03-29 JP JP3507370A patent/JPH0680489B2/ja not_active Expired - Lifetime
  • 1991-03-29 DE DE69132271T patent/DE69132271T2/de not_active Expired - Fee Related
  • 1991-03-29 WO PCT/US1991/002040 patent/WO1991017495A1/en not_active Ceased
  • 1991-03-29 EP EP91908085A patent/EP0545927B1/de not_active Expired - Lifetime
  • 1991-03-29 EP EP19910907170 patent/EP0481031A4/en not_active Withdrawn

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