EP0702849A1 - Matrice prediffusee a cellules souples - Google Patents

Matrice prediffusee a cellules souples

Info

Publication number
EP0702849A1
EP0702849A1 EP94919331A EP94919331A EP0702849A1 EP 0702849 A1 EP0702849 A1 EP 0702849A1 EP 94919331 A EP94919331 A EP 94919331A EP 94919331 A EP94919331 A EP 94919331A EP 0702849 A1 EP0702849 A1 EP 0702849A1
Authority
EP
European Patent Office
Prior art keywords
polycrystalline silicon
gate array
cells
cell
diffusion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP94919331A
Other languages
German (de)
English (en)
Inventor
Walter F. Bridgewater
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Semiconductor Corp
Original Assignee
National Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Semiconductor Corp filed Critical National Semiconductor Corp
Publication of EP0702849A1 publication Critical patent/EP0702849A1/fr
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/998—Input and output buffer/driver structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/416—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials of highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers

Definitions

  • This invention pertains to integrated circuits, and more particularly to gate array architectures in which an array of electronic gates are fabricated in a base array, and which are then programmed utilizing personalization layers in order to provide a specific function.
  • bonding pads are fixed when the base array is laid out, thus requiring a redesign of the base array if it is desired to place a device into a different package type, having a different lead frame layout.
  • the input/output (I/O) cells are fixed in the array, and the bonding pads may be placed as desired, with appropriate metallization interconnects made between the bonding pads and their associated I/O cells.
  • U.S. Patent No. 4,893,170 describes an integrated circuit in which a plurality of interconnect layers are utilized. At least one of the interconnected layers runs in a vertical direction along the surface of the integrated circuit, and the remaining interconnect layers run in a horizontal direction on the surface of the integrated circuit device. Generally, due to potential problems with congestion, alternate levels of electrical interconnects run perpendicular to each other.
  • the 170 patent describes that either first and second layers of vertical interconnects or first and second layers of horizontal interconnects are used to connect to the input terminals and output terminals, respectively, of the various logic cells contained within the gate array.
  • one layer of polycrystalline silicon is used to form the gate electrodes of MOS transistors within the logic cells of the gate array, and also serves to provide electrical interconnection between the logic cells and the metal layers of electrical interconnection located in a dedicated routing channel.
  • U.S. Patent No. 4,602,270 describes a gate array in which the locations for contacts between the underlying silicon and a polycrystalline silicon layer, or between the polycrystalline silicon layer and the first layer of interconnect metallization, are predefined, although the actual use of a contact in a predefined location is dependent on the electrical function to be performed by a particular gate array.
  • U.S. Patent No. 4,811,073 describes a gate array which contains one or more power supply buses encircling the core of the gate array and within the region defined by the I/O cells.
  • the power lines contained within the core of the array are connected to the power supply bus rings, as are the power supply connections to the I/O cells. In this manner, the pitch of the I/O cells and the pitch of the cells within the core of the gate array need not be identical.
  • U.S. Patent No. 4,809,029 describes a gate array which includes a plurality of I/O cell regions, each having an associated general purpose cell array region.
  • the I/O general purpose cell arrays can be used for fabricating logic particularly useful with a given I/O circuit, for example for testing purposes.
  • novel gate arrays incorporate simple, but ingenious architectural improvements over prior art gate arrays, including prior art sea-of-gate arrays.
  • a programmable layer of polycrystalline silicon is utilized to improve logic and RAM densities as compared with prior art gate arrays which utilize a similar number of metallization layers such that either vertically or horizontally oriented layers of metallization are used to make electrical contact to the input and/or output terminals of gate array cells.
  • the programmable layer of polycrystalline silicon is capable of providing electrical connections within a particular logic cell, without requiring the use of electrical interconnections within a dedicated routing .channel. This allows increased density of the gate array.
  • a gate array is fabricated utilizing two layers of metallization having densities comparable to that which is sometimes capable of being achieved utilizing prior art gate arrays utilizing three layers of metaltization.
  • teachings of this invention provide gate arrays utilizing three layers of metallization which have densities comparable to prior art gate arrays which would require four layers of metallization.
  • Constructing gate arrays in accordance with the teachings of this invention also provides the highest RAM densities available in a gate array architecture.
  • programmable polycrystalline silicon polycrystalline silicon contact connections are placed only where needed, avoiding the need to leave space between adjacent polycrystalline silicon lines for all potential contact connections. This results in approximately as 2:1 reduction in cell size.
  • transistors in the gate array are packed closer together than taught in the prior art as a result of the use of a programmable polycrystalline silicon layer.
  • the dedicated space needed for contact sites that are necessary in prior art sea-of-gate arrays is not required. This allows for more logic and higher gate densities for a given process geometry and a given number of metallization layers.
  • gate arrays are fabricated which accommodate mask programmable pad pitches (spacing between bonding pads), tailored for tape automated binding (TAB), gold, or aluminum bonding.
  • Figure la is a schematic diagram of a prior art 5- input NAND gate
  • Figure lb is a layout of the circuit of Figure la utilizing the prior art sea-of-gates technology
  • Figure lc is a plan view depicting the layout of the circuit of Figure la in accordance with one embodiment of this invention.
  • Figure 2 is a plan view of a portion of a gate array structure constructed in accordance with the teaching of this invention.
  • Figure 3a is a plan view depicting a RAM cell laid out utilizing the prior art sea ' -of-gates technology
  • Figure 3b is a plan view depicting the layout of one embodiment of a RAM cell constructed in accordance with the teachings of this invention
  • Figure 4 is a plan view of a portion of a gate array constructed in accordance with the teachings of this invention
  • Figure 5 is a plan view of a portion of a gate array constructed in accordance with the teachings of this invention.
  • FIG. 6 is a plan view depicting certain features of the I/O structure in accordance with the teachings of this invention.
  • Figure 7 is a plan view depicting certain features of the I/O structure and other features of one embodiment of this invention.
  • a gate array which includes a plurality of pairs of diffusion strips, each pair including an N and a P diffusion strip.
  • the N and P diffusion strips are laterally separated by an interdiffusion track.
  • Dedicated routing channels are provided adjacent each diffusion strip opposite the interdiffusion track.
  • One or more cells are formed within a pair of diffusion strips and the associated portion of the interdiffusion track, each cell performing a desired electrical function.
  • a cell is formed by determining the number of polycrystalline silicon gate electrodes required to form the necessary number of transistors to implement the electrical function. These polycrystalline silicon gate electrodes are then placed with minimum spacing, only leaving sufficient room for contacts where it is known they will be specifically needed.
  • each cell is terminated on each end in a portion of the diffusion regions which are connected to a source of power, such diffusion isolation regions being shared by two adjacent cells, if desired.
  • the diffusion strips are then formed, using the polycrystalline silicon as a partial mask, providing self aligned source/drain regions. In this manner, cells are formed as part of the personalization process, each cell consuming a minimum amount of the length of the diffusion strips.
  • dedicated transistors are not formed prior to personalization.
  • RAM cells are formed in a similar manner, but need not be terminated in isolation diffusion regions within the RAM, so that word lines and/or bit lines are conveniently formed.
  • Gate arrays constructed in accordance with the teachings of this invention provide distinct advantages over prior art gate array architectures, including prior art sea-of-gate architecture, particularly with respect to gate utilization.
  • Prior art sea-of-gates architectures typically achieve gate utilizations on the order of 40 percent.
  • gate arrays constructed in accordance with the teachings of this invention depending on the specific circuit design desired by the end user, achieve gate utilization of between approximately 50 percent and 80 percent.
  • a layer of polycrystalline silicon is used not only for the purposes of forming gate electrodes or providing electrical connection between a gate array cell and a routing channel, as is known in the prior art, but also for providing a certain amount of routing within a gate array cell without requiring the use of dedicated routing channels within which transistors cannot be formed.
  • One embodiment of this invention contains 250K gross gates. This array could, for example, accommodate a design of 58K gates of logic and another 59K bits of RAM. This is equivalent to 164K usable gates.
  • gate arrays are fabricated using a 0.8 micron L-effective, ( 1-micron drawn) CMOS process .
  • devices are fabricated using a library of cells common to gate arrays as well as standard cells fabricated from a standard cell library.
  • This library includes a large number of core macros (i.e. large cells performing relatively complex electrical functions), small scale integration (SSI), and medium scale integration (MSI) functions, a variety of different I/O cells, and can be integrated with module-generated, high-density ROM and RAM.
  • core macros i.e. large cells performing relatively complex electrical functions
  • SSI small scale integration
  • MSI medium scale integration
  • Figure la is a schematic diagram of a typical prior art 5-input NAND gate.
  • the layout shown in Figure lb includes space for all possible contacts, thereby wasting a significant amount of area.
  • the layout depicted in Figure lc made in accordance with the teachings of this invention, provides programmable polycrystalline silicon strips 9 which serve as gate electrodes having minimum spacings in areas 10 and 11 where contacts are not needed.
  • FIG. 2 is a composite view of one example of an electronic circuit constructed from a portion of gate array core in accordance with the teachings of this invention.
  • Gate array circuit 100 includes P+ diffusion strip 101 and N+ diffusion strip 102.
  • a plurality of polycrystalline silicon gate electrodes 105 are formed within P+ diffusion strip and N+ di fusion strip 102 such that a plurality of transistors are formed therein.
  • polycrystalline silicon gate electrodes are fabricated prior to formation of diffusion 101 and 102, thereby providing source/drain regions such as regions 106 and 107 which are self aligned to their associated polycrystalline silicon gate electrodes.
  • P+ diffusion strip 101 is made wider than N+ diffusion strip 102 in order to match the speed of the N channel and P channel transistors.
  • N+ diffusion contacts 103 serve to electrically connect desired portions of diffusion strip 101 to supply voltage VDD through a first layer of metallization 110, such as aluminum or an alloy thereof.
  • metallization 110 is formed of tungsten or an alloy thereof, which provides greater planarity which allows stacked vias to be placed over contacts.
  • N+ diffusion contacts 104 are used to connect desired portions of N+ diffusion strip 102 to supply voltage VSS through first layer metallization 111.
  • gate array circuitry 100 are electrically interconnected by the use of programmable polycrystalline silicon interconnects which do not need to leave the cell area itself.
  • polycrystalline silicon interconnect 108 serves to electrically connect two adjacent polycrystalline silicon gate electrodes within N+ diffusion strip 102.
  • polycrystalline silicon interconnect 109 serves to electrically connect two polycrystalline gate electrodes within N+ diffusion strip 102 with two polycrystalline silicon gate electrodes within P+ diffusion strip 101.
  • the polycrystalline silicon need not exit the cell region itself for location within dedicated routing channel 120 which, in the prior art, would then be used to interconnect the polycrystalline silicon to a metallization interconnect layer.
  • a polycrystalline silicon interconnect is used within the cell area itself, thereby reducing the need for metallization interconnects over the cell, thus allowing this area to be used for intercell routing.
  • Metal 1 routes run generally horizontally over the cells (i.e., in locations 118-1 through 118-5) and metal 2 routes run generally vertically across them (i.e., in locations 119-1 through 119-5). If metal 1 is used for making all connects between transistors and gates (as in the prior art), less of the metal 1 interconnection resource is available for longer routes going over the cells. Also shown in the embodiment of Figure 2 are substrate/well contacts 112 and 113, which allow VDD bus 110 to be connected to N well substrate and VSS bus 111 to be connected to P substrate, respectively.
  • a plurality of substrate/well contacts 112 and 113 are capable of being provided, although selected ones may be eliminated in order to provide room for polycrystalline silicon interconnects beneath power busses 110 and 111 if desired, thereby further- increasing the ability to route within the cell itself rather than requiring dedicated rotating channels 120 or further consuming routing resources within the cell.
  • polycrystalline silicon interconnect 121 may be used, if desired, to interconnect two polycrystalline silicon gates within P+ diffusion strip 101.
  • Polycrystalline silicon interconnect 121 lies beneath first layer metallization VDD bus 110, which is fabricated to be relatively wide in order to have sufficient current carrying capacity.
  • electrical interconnect 114 fabricated from a first layer of metallization.
  • Metallization interconnect 114 serves to electrically connect source/drain region 107 lying within N+ diffusion strip 102 with a similar source/drain region lying within P+ diffusion strip 101, through first layer metallization to diffusion contacts 115.
  • First layer metallization interconnect 114 is also shown connected to metallization via 117, in the event a second layer of metallization (not shown) is to be electrically connected to first layer metallization interconnect 114.
  • inputs and outputs to a cell may be provided to either first or second metallization.
  • a plurality of potential first layer metallization routing paths 118-1 through 118-5 lie within cell 100 above P+ diffusion strip 101.
  • a similar set of unnumbered potential first layer metallization routing channels exist overlying N+ diffusion strip 102. These potential routing channels run in a horizontal direction, although first layer metallization is capable of being fabricated in either a horizontal or vertical direction.
  • first layer metallization interconnects running in the horizontal direction overlying diffusion strips 101 and 102 ⁇ routing density is enhanced. It is shown by the embodiment of Figure 2 that the use of polycrystalline silicon interconnects for routing within the cell, rather than simply for making entry into dedicated routing channel 120, minimizes the consumption of routing resources within dedicated routing channel 120.
  • interdiffusion track 147 is capable of being used to make contact to polycrystalline silicon regions.
  • first layer metallization to polycrystalline silicon contact 116 Similar polycrystalline silicon contacts can be used for connection to levels of metallization higher than the first layer of metallization. It is also possible to make contact to polycrystalline silicon over diffused regions 101 and 102, although this has the disadvantage of increasing capacitance.
  • Figure 2 depicts the layout of a cell within long strips 101 and 102 of diffusion which extends beyond cell 100 shown in Figure 2.
  • Cell 100 is terminated on either end by isolation diffusion regions making connection to power.
  • isolation diffusion region 106 is connected to power bus 111 through contact 104. This serves -to provide electrical isolation between cell 100 and adjacent cells, which are formed on either side of cell 100, as diffusion strips 101 and 102 extend beyond cell 100.
  • Increased density is afforded in accordance with the teachings of this invention by allowing adjacent cells to share in terminating diffused area 106, for example.
  • polycrystalline silicon stub 148 extends from within the cell, beneath power bus metallization 110, into routing channel 120. There it is connected to first level metallization interconnect 150 through via contact 149. As shown in Figure 2, a substrate contact 112 is not formed beneath polycrystalline silicon stub 148.
  • Polycrystalline silicon has a higher impedance than metal and thus stub routes are limited to no more than, for example, approximately 50 microns. This minimizes the delay associated with polycrystalline silicon RC time constant.
  • a benchmark design with worst case requirements for routing resources was utilized.
  • the design contained a large amount (60,000 gates) of low level logic, such as NAND and NOR gates, and wide buses.
  • the comparison was made between the routing resources available on a prior art 2-layer metal sea-of-gates array, a prior art 3-layer metal sea-of-gates array, and a 2-layer metal array constructed in accordance with the teachings of this invention. All other things were equal in the comparison, such as the router, design rules, etc.
  • Implementing the design using a prior art 2-layer metal sea-of-gates array required an integrated circuit die with 576 mils on a side.
  • one embodiment also provides on-chip
  • RAM is implemented with the same base cell as surrounding logic, allowing complete flexibility in RAM width, depth, the number of RAMs, and their location within the integrated circuit. This also improves the packing density of logic and increases the amount of RAM possible within a gate array of a given physical size.
  • Table 1 shows a process comparison between National Semiconductor's double layer metal process, a typical prior art double layer metal process, a typical prior art three layer metal process, a typical prior art standard cell device, and the present invention.
  • the "X"s indicate the number of process steps which must be performed following the first process step pertaining to personalization of the device, and the asterisks indicate such process steps which are not themselves personalization steps.
  • a novel I/O design is utilized which solves a significant cause of poor performance on printed circuit boards.
  • I/O on most prior art gate arrays are TTL- compatible. TTL sinks more current than it sources, which can lead to impedance mismatches on printed circuit board routes.
  • one embodiment of the present invention includes output buffers that are optimized to drive terminated printed circuit board traces of specified impedances to provide good transmission-line driving characteristics.
  • I/O buffers are designed and fabricated in order to source and sink the same amount of current. This gives improved waveform characteristics when the gate array is mounted on a printed circuit board for use in a system.
  • I/O pins are programmable as input/output, bidirectional, power and ground.
  • a gate array is provided having both normal and slew rate controlled outputs.
  • the slew rate controlled outputs are slower but allow more outputs to switch simultaneously, a good feature on designs with wide buses.
  • Slew rate controlled outputs are also well suited for designs that are I/O limited and cannot afford many power pins. Slower slew rates produce less di/dt at the power pins, and therefore less power, supply noise.
  • novel gate arrays are provided which also include small I/O gate arrays associated with one or more I/O pins.
  • I/O gate arrays are capable of providing approximately 70 transistors, in the same manner as taught with regard to the gate array in the core of the device.
  • I/O gate arrays allow the designer to implement test circuitry and methods, for example IEEE 1149.1 Joint Test Action Group (JTAG) boundary scan, without using gates i.n the core of the array.
  • JTAG Joint Test Action Group
  • the I/O gate arrays are intended specifically for implementing testing features such as boundary scan, and do not detract from the availability of resources in the core of the device. Thus, the designer need not consume core resources when implementing boundary scan.
  • Figure 4 is a plan view depicting the layout of another portion of a gate array constructed in accordance with the teachings of this invention. Shown in Figure 4 are, for example, diffusion strips 619-1 through 619-4, routing channels 620-1 and 620-2 and interdiffusion track 621. Intracell polycrystalline silicon routing trace 601 is located beneath power bus 614 in a region free from substrate contact 615.
  • Cell 600 includes a number of transistors defined by polycrystalline silicon and associated source/drain regions within diffusion strips 619-2 and 619-3.
  • Cell 600 is terminated on each end by diffusion isolation regions 627-1 through 627-4, which are connected to either power bus 614 or 624.
  • Polycrystalline stub connector 602 extends into routing channel 620-2 for connection through contact 603 to second layer metallization 605, which in turn is connected through via 630 to first layer metallization interconnect 631.
  • First layer metallization interconnects such as interconnect 632 are routed within interdiffusion track 621, for example, connection to polycrystalline silicon within the cell through contact 606.
  • FIG. 5 is a plan view depicting another portion of a gate array 700 constructed in accordance with the teachings of this invention, with numerical designations corresponding to similar features in the embodiment of
  • gate array 700 includes cell 780 and cell 781, both formed from portions of diffusion strips 719-2 and 719-3, and each of which are terminated with diffusion isolation regions connected to one of the power busses.
  • cells 780 and 781 are defined by the personalization process, and each transistor within cells 780 and 781 are defined to be of minimum size by the placement of polycrystalline silicon as a step in the personalization process. Space for contacts is provided only where it is certain a contact is needed in order to provide the electrical interconnections required to achieve the electrical function of each cell.
  • the ⁇ ize of each cell i.e. the amount of the length of diffusion strips 719-2 and 719-3 consumed by each cell, is specifically provided as the minimum required to achieve the electrical function of each cell.
  • Figure 6 is a plan view depicting one embodiment of this invention showing a basic I/O structure 200 located adjacent to edge 201 of the integrated circuit die.
  • N channel I/O array 203 includes a plurality of polycrystalline silicon gates 207 formed within N+ diffusion strips 205-1 through 205-2.
  • polycrystalline silicon gate electrodes 207 are formed prior to the diffusion of N+ diffusion strips 205-1 and 205-2, thereby forming source/drain regions 209-1 and 209-2 which are self aligned to their associated polycrystalline silicon gate 207.
  • P channel I/ ⁇ array 204 is fabricated in a similar fashion.
  • N channel I/O array 203 and P channel I/O array 204 are fabricated such that their diffusion strips 205-1, 205- 2, 206-1, 206-2 are substantially perpendicular to edge 201 of the integrated circuit and thus their polycrystalline silicon gate electrodes 207 and 208 are substantially parallel with edge 201 of the integrated circuit.
  • any desired number of transistors may be fabricated in N channel I/O array 203 and P channel I/O array 204 simply by increasing their length inward from edge 201 of the integrated circuit. While this consumes substantially the same integrated circuit die area as if oriented differently, it does not effect the pitch associated with I/O structure 200.
  • FIG. 6 shows two diffusion strips associated with each of N channel I/O array 203 and P channel I/O array 204 any desired number of diffusion strips can be formed within I/O arrays 203 and 204.
  • I/O arrays 203 and 204 can be located side by side so long as their combined widths provide an acceptable I/O pitch.
  • N channel and/or P channel transistors used for constructing the actual I/O buffer circuitry, as well as electrostatic discharge (ESD) protection, as is well known in the art.
  • FIG. 7 is a plan view of portion of a gate array constructed in accordance with the teachings of this invention, again generally depicting the bonding pads and I/O structure.
  • Gate array 300 includes a plurality of bonding pads 202 and their associated I/O buffers 519. In the interior of gate array 300 lies logic core 303. Also shown in Figure 7 are N channel diffusion strips 203-1 and 203-2, and P channel diffusion strips 204-1 through 204-2. These are used for forming gates associated with bonding pad 202, as previously described with regard to the embodiment of Figure 6. Of interest, the pitch associated with I/O buffer 519 is substantially equal to the pitch associated with bonding pad 202, as well as the pitch associated with diffusion strips 203-1, 203-2, 204-1, and 204-2.
  • I/O buffer 519 By arranging the transistors within I/O buffer 519 in the same orientation as previously described with regard to the I/O array, transistors formed within the diffusion strips, additional transistors may be formed within I/O buffer 519 by increasing the depth of I/O buffer 519 rather than its width, thereby not increasing its pitch. Also shown in the embodiment of Figure 7 are "the power connections to I/O buffer 519. In this embodiment, I/O buffer 519 is formed symmetrically with respect to its power in that one VSS connection 527 is located along its central axis having a size sufficient for the power needs of I/O buffer 527. Two VDD power connections 526 are provided on either edge of I/O buffer 519, thereby collectively providing sufficient VDD power capacity to I/O buffer 519.
  • VDD power connections 526 of adjacent I/O buffer 519 abut, and thus are contacted by a single metallization layer.
  • the power busses (not shown) which contact VSS terminal 527 and VDD terminals 526 are also capable of being extended over the abutting edges of diffusion strips 204-1 and 204-2; and 203-1 and 203-2 (of adjacent I/O gate arrays), respectively. This allows for convenient routing of power to both I/O buffers 519 and the I/O gate arrays.
  • the VSS and VDD power busses may extend to the other edge of the die and connect to their counterparts in the I/O buffers on the opposite edge of the integrated circuit.
  • the same power busses which extend over the core of the gate array in order to connect to I/O buffers on opposite edges of the integrated circuit can also be used to connect to the first layer metallization power busses within the various cells of the gate array. This obviates the need for a dedicated power routing ring around the core of the array just interior of the I/O circuitry, providing a significant savings in integrated circuit area. This is accomplished while requiring a single layout for the I/O circuitry, since it is symmetrical with respect to its power access.
  • the normally unused space 304 near the corners of the integrated circuit is put to use.
  • vertical PNP transistors are fabricated in region 304.
  • Vertical PNP transistors are capable of being fabricated during an MOS fabrication process without additional process steps .
  • These vertical PNP transistors are capable of being used for any desired purpose, including their use to form bandgap voltage references, which are particularly useful when implementing analog functions in gate array 300.
  • the polycrystalline silicon layers are programmable (as described previously with regard to Figure 2)
  • transistors are capable of being provided having programmable gate lengths. This is particularly useful for forming analog functions, where current ratios are of importance and are easily provided as a function of ratios of gate lengths of various transistors.
  • the polycrystalline silicon layer is programmable, diffused resistors can be provided, including matched sets of diffused resisors, which are also useful in analog functions.
  • the fused regions can, if not otherwise diffused, be used to fabricate diffused resistors, also useful in performing analog functions.
  • capacitors are easily fabricated of desired capacitances by fabricating a polycrystalline silicon layer of a desired size over a diffused area, with the polycrystalline silicon serving as one plate of the capacitor and the diffused region serving as the other plate of the capacitor.
  • Appendix A to the specification is a document outlining certain features of the claimed invention
  • Appendix B is a gate array design manual which also describes certain features of the present invention.
  • Appendix C is additional information describing certain features of this invention.

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  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

Nouvelles matrices prédiffusées qui présentent des caractéristiques architecturales simples mais ingénieuses. Une couche programmable de silicium polycristallin est utilisée pour améliorer les densités logique et de mémoire vive. Ladite couche programmable de silicium polycristallin est capable de fournir des connexions électriques au sein d'une cellule logique particulière, sans nécessiter l'utilisation d'interconnexions électriques dans une voie d'acheminement exclusive. Cela permet d'augmenter la densité de la matrice prédiffusée. Grâce au silicium polycristallin programmable, il est possible de placer des connexions de contact en silicium polycristallin uniquement là où elles sont nécessaires, ce qui évite le besoin de laisser de l'espace entre des rangées de silicium polycristallin adjacentes pour toutes les connexions de contact potentielles.
EP94919331A 1993-06-07 1994-06-03 Matrice prediffusee a cellules souples Withdrawn EP0702849A1 (fr)

Applications Claiming Priority (3)

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US74002 1979-09-10
US7400293A 1993-06-07 1993-06-07
PCT/US1994/006214 WO1994029902A1 (fr) 1993-06-07 1994-06-03 Matrice prediffusee a cellules souples

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JP5357476B2 (ja) * 2008-09-11 2013-12-04 ルネサスエレクトロニクス株式会社 半導体集積回路装置の製造方法
US7956438B2 (en) * 2008-11-21 2011-06-07 Xilinx, Inc. Integrated capacitor with interlinked lateral fins

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JPS57211247A (en) * 1981-06-22 1982-12-25 Hitachi Ltd Semiconductor integrated circuit device
JPS5835963A (ja) * 1981-08-28 1983-03-02 Fujitsu Ltd 集積回路装置
JPS6072247A (ja) * 1983-09-28 1985-04-24 Toshiba Corp 半導体集積回路装置
JPH01168042A (ja) * 1987-12-23 1989-07-03 Sharp Corp 半導体集積回路装置

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KR960702947A (ko) 1996-05-23
WO1994029902A1 (fr) 1994-12-22
JPH09507000A (ja) 1997-07-08

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