EP0707344B1 - Halbleiteranordnung mit einer dünnen Polysilicium-Schicht und Verfahren zur Herstellung - Google Patents

Halbleiteranordnung mit einer dünnen Polysilicium-Schicht und Verfahren zur Herstellung Download PDF

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Publication number
EP0707344B1
EP0707344B1 EP95114554A EP95114554A EP0707344B1 EP 0707344 B1 EP0707344 B1 EP 0707344B1 EP 95114554 A EP95114554 A EP 95114554A EP 95114554 A EP95114554 A EP 95114554A EP 0707344 B1 EP0707344 B1 EP 0707344B1
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Prior art keywords
thin film
film
gas
crystal
silicon
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French (fr)
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EP0707344A3 (de
EP0707344A2 (de
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Hideo Miura
Shunji Moribe
Hisayuki Kato
Atsuyoshi Koike
Shuji Ikeda
Asao Nishimura
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Hitachi Ltd
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Hitachi Ltd
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    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
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Definitions

  • This invention relates to method for producing a thin film electrode of a semiconductor device prevented from changes of internal stress in a silicon thin film and generation of crystal defects caused by the changes of internal stress.
  • a silicon thin film is used as electrodes and/or a wiring material. Since the silicon thin film is a semiconductor material, it is necessary to reduce electric resistance when used as a wiring material. In general, it is doped with an element of group III or V (e.g. B, P, As, etc.) by diffusion. In the doping with such an impurity, there has been employed thermal diffusion from film surface or ion implantation.
  • group III or V e.g. B, P, As, etc.
  • JP-A-03 070 126 describes a method for production of an electrode having a low electric resistance by forming a silicon dioxide film and a gate oxide film on a p-type silicon substrate, adding an impurity to a channel section, depositing an amorphous silicon film for a gate electrode by a CVD method, heat treating at 600°C or higher to carry out polycrystallisation, adding n-type impurity and activation of the impurity by subsequent heat treatment.
  • a polycrystalline silicon thin film is formed the crystal grains of which are oriented with their [111] axes in the vertical direction of the substrate surface.
  • US 5,318,919 describes a manufacturing method of a thin film transistor using an in-situ doping technique.
  • a pure amorphous silicon layer having a thickness of approximately 1 ⁇ m and an in-situ doped n-type conductive amorphous silicon layer are laminated on a glass substrate.
  • the laminated layers are annealed at temperatures below 600° to result in a polycrystalline silicon film.
  • a part of the surface of the polycrystalline silicon film is removed by etching where the gate electrode is to be formed, followed by formation of an insulative film. Thereafter, a metallic gate electrode is formed on the insulative film.
  • the polycrystalline silicon thin film can be formed at low temperatures using a cheap glass substrate without implantation of a dopant.
  • DE 41 38 057 Al describes a semiconducor device having a polycrystalline silicon layer as a gate electrode the crystal grains of which are oriented in a particular direction what is achieved by the conventional LPCVD method including the control of the deposition temperature in the range of 550 to 620°C.
  • GB 2 254 960 A describes a conventional LPCVD process which is used to deposit an amorphous silicon layer at temperatures of 510 to 560°C and an overlying polycrystalline silicon layer at a higher temperature of 610 to 640°C on a gate oxide layer of a substrate.
  • the layer structure is converted into polycrystalline silicon by annealing.
  • the resulting upper polysilicon layer has a larger grain size as compared to the lower polysilicon layer and the diffusion of P- ions which are incorporated by the thermal diffusion is minimised.
  • the method of the invention provides a semiconductor device comprising a semiconductor substrate, an underlying film formed thereon and a silicon thin film doped with an impurity selected from group III and V elements and formed on the underlying film, crystal grains of said silicon thin film having mainly a columnar structure grown from an interface of the underlying film to a surface of the silicon thin film, and a crystal orientation on film surfaces of at least 60% of the individual crystal grains being in an uniform direction.
  • the present invention also provides a process for producing a semiconductor device, which comprises forming an underlying film on a semiconductor substrate, and forming a silicon thin film on the underlying film by depositing a silicon film having no impurity from a SiH 4 gas or a Si 2 H 6 gas to a thickness of 1 nm or more, followed by deposition of the silicon film doped with an impurity selected from group III and V elements.
  • a silicon film having no impurity from a SiH 4 gas or a Si 2 H 6 gas to a thickness of 1 nm or more
  • an impurity selected from group III and V elements When an amorphous silicon thin film is deposited, heat treatment is conducted to finally provide a polycrystalline silicon thin film.
  • the present invention still further provides a process for producing a silicon thin film, which comprises introducing into a reaction chamber a raw material gas selected from SiH 4 gas and Si 2 H 6 gas to deposit a silicon film having no impurity to a thickness of 1 to 10 nm, followed by introduction of an impurity gas selected from group III and V elements together with the raw material gas to deposit a silicon film doped with the impurity.
  • a process for producing a silicon thin film which comprises introducing into a reaction chamber a raw material gas selected from SiH 4 gas and Si 2 H 6 gas to deposit a silicon film having no impurity to a thickness of 1 to 10 nm, followed by introduction of an impurity gas selected from group III and V elements together with the raw material gas to deposit a silicon film doped with the impurity.
  • an impurity gas selected from group III and V elements together with the raw material gas to deposit a silicon film doped with the impurity.
  • Fig. 1 is a cross-sectional view of one example of the semiconductor device immediately after the film deposition according to the present invention.
  • Fig. 2 is a cross-sectional view of the same example of the semiconductor device after heat treatment according to the present invention.
  • Fig. 3 is an electron microscope photograph showing the structure of growing crystal at a cross-section of P-doped amorphous silicon thin film.
  • Fig. 4 is an electron microscope photograph showing the structure of growing crystal at a plane of P-doped amorphous silicon thin film.
  • Fig. 5 is an electron microscope photograph showing the structure of growing crystal at a cross-section of P-doped amorphous silicon thin film when the non-doped layer is formed.
  • Fig. 6 is an electron microscope photograph showing the structure of growing crystal at a plate of P-doped amorphous silicon thin film when the non-doped layer is formed.
  • Fig. 7 is a flow chart explaining one example of the process for depositing the thin film.
  • Fig. 8 is a cross-sectional view of a further example of the semiconductor device immediately after the film deposition according to the present invention.
  • Fig. 9 is a cross-sectional view of a transistor according to the present invention.
  • Fig. 10 is a cross-sectional view of a gate electrode according to the present invention.
  • Fig. 11 is a cross-sectional view of a flash memory according to the present invention.
  • Fig. 12 is a schematic view of a chemical vapor deposition apparatus according to the present invention.
  • the present inventors found that the impurity concentration and its distribution (or differences in the concentration) near the interface between the amorphous (including fine crystalline state) silicon thin film and the underlying film (e.g. silicon dioxide film) is controlled so as to make the state for generating crystal nucleuses almost uniform and to make the crystal state (crystal grain size and crystal orientation) of polycrystalline film after heat treatment stable (or uniform).
  • the amorphous (including fine crystalline state) silicon thin film and the underlying film e.g. silicon dioxide film
  • the present inventors found that it is effective to form a layer not containing an impurity near the interface of underlying film (i.e. on the underlying film), near the interface of underlying film (i.e. on the underlying film).
  • the direction of crystal plane of polycrystalline layer after crystallization becomes almost uniform, so that the above-mentioned object can be attained due to stabilization of crystal state.
  • the semiconductor device resulting from the method the present invention comprises a semiconductor substrate, an underlying film formed thereon and a polycrystalline silicon thin film doped with an impurity selected from group III and V elements and formed on the underlying film, crystal grains of said silicon thin film having mainly a columnar structure grown from an interface of the underlying film to a surface of the silicon thin film, and a crystal orientation on film surfaces of individual crystal grains being in an almost uniform direction.
  • the semiconductor substrate there can be used conventional ones such as a silicon single crystal substrate, a so-called SOI (silicon-on-insulator) substrate, a wafer obtained by epitaxial growth, and the like.
  • the underlying film there can be used films of SiO 2 , SiN, N 2 O (oxynitride), Ta 2 O 5 , ferroelectric metals of PZT (complex of oxides of Pb, Zr and Ti), or a laminate structure thereof.
  • the impurity there can be used an element selected from group III and V elements such as P (phosphorus), B (boron), As (arsenic), etc. singly or as a mixture thereof.
  • the expression "in an almost uniform direction” means that crystal graphic direction of polycrystalline grains is the same in 60% or more, preferably 80% or more, more preferably 90% or more.
  • a gate oxide film is used as the underlying film and a gate electrode is made from a polycrystalline silicon thin film.
  • the semiconductor device comprises a silicon single crystal substrate, a gate oxide film and a gate electrode formed on the gate oxide film, said gate electrode being made from a silicon thin film doped with an impurity selected from group III and V elements, said silicon thin film being deposited on the gate oxide film, crystal gains of said silicon thin film having mainly a columnar structure grown from an interface of the gate oxide film to a surface of the silicon thin film, and a crystal orientation of film surfaces of individual crystal grains being in an almost uniform direction.
  • Such a semiconductor device can be produced by forming an underlying film on a semiconductor substrate using a conventional method, and forming a silicon thin film on the underlying film by depositing a silicon film having no impurity from a raw material gas such as a SiH 4 gas or a Si 2 H 6 gas to a thickness of 1 nm or more, followed by deposition of the silicon film doped with an impurity selected from group III and V elements, followed by heat treatment at 550°C to 1000°C when the deposited silicon film is an amorphous silicon film to give a polycrystalline silicon thin film.
  • a raw material gas such as a SiH 4 gas or a Si 2 H 6 gas
  • the deposition of silicon thin film is carried out at 500°C to 700°C in the case of polycrystalline silicon thin film, or at 500°C to 600°C in the case of amorphous silicon thin film.
  • the average concentration of impurity in the thin film is about 10 18 - 10 21 number of atom per cm 3
  • the silicon concentration in the thin film is about 5 ⁇ 10 22 number of atom per cm 3 .
  • the amorphous silicon thin film is formed, for example, on a thermal oxide film of silicon (as an underlying film) in about 100 nm thick. A part of amorphous state is found to be crystallized.
  • the crystal grains grown in the shape of ellipsoid are silicon single crystals and the (311) plane of silicon crystal is grown to the top surface of the thin film. This is confirmed by an electron diffraction method.
  • the crystal grains grown in the shape of asteroid are polycrystalline silicon and each hand portion of the asteroid shows a sing crystal state having the (111) crystal plane. This is also confirmed by the electron diffraction method.
  • the presence of such thin film in the semi-conductor device is not preferable. It is desirable that the crystal orientation is almost in a uniform direction. Further, internal stress state in the thin film changes depending on orientation of crystal plane.
  • the internal stress value is the highest when the (111) crystal plane grows and decreases with an increase of the crystal plane indices (the direction from the (111) plane to the (211) plane and (311) plane). Measured value of internal stress is 1200 MPa when the crystal plane index is at the (111) plane, 1000 MPa at the (211) plane, and 800 MPa at the (311) plane. This is because in the silicon crystals since the (111) crystal plane has the highest atomic density at the highest denseness plane, the shrinkage of the thin film becomes larger relatively compared with the case of growing other crystal plane.
  • the above-mentioned internal stress value in the thin film is in the case when a simple crystal plane grows.
  • an intermediate value will be taken depending on occupying rates of crystal plane directions of individual crystal grains.
  • the (111) crystal plane which is to take a high internal stress value grows, it is possible to prevent the generation of failure caused by the internal stress of whole of the semiconductor device by changing a semiconductor device structure or a combination of materials used.
  • the stress value to be generated is known, it is possible to avoid the case of impossible to use.
  • the important thing is to establish the homogenuity of the thin film (including variation of stress value) by avoiding the admixed state of crystal grains having different grown crystal planes.
  • the crystals grow as follows.
  • the crystal growth of the silicon thin film can be controlled by positively controlling the P concentration near the interface of underlying layer.
  • this thin film deposition method is very important from the viewpoint of controlling crystal planes of polycrystalline thin film.
  • the semiconductor device using a silicon thin film doped with an impurity of group III or V elements is characterized in that the semiconductor device is produced by controlling the impurity concentration near the interface between the underlying film and the silicon thin film to remarkably low (preferably zero or almost zero) compared with the average impurity concentration in the thin film, and as a result, the crystal plane direction in the polycrystalline silicon thin film after crystallization is in an almost uniform direction.
  • the chemical vapor deposition apparatus suitable for producing such a silicon thin film according to the present invention comprises
  • This Example shows the case of not introducing an impurity near the interface of underlying film as a method of controlling the impurity concentration and distribution thereof near the interface of underlying film.
  • FIG. 1 is a cross-sectional view immediately after the deposition of thin film (after patterning).
  • Fig. 2 is a cross-sectional view after formation of a polycrystalline film and formation of an insulating film 6.
  • MOS metal-oxide-semiconductor
  • numeral 1 denotes a silicon substrate
  • numeral 2 denotes a silicon oxide film
  • numeral 3 denotes a non-doped amorphous silicon layer
  • numeral 4 denotes a P-doped amorphous silicon layer
  • numeral 5 denotes a P-doped polycrystalline silicon film
  • numeral 30 denotes an interface of underlying film.
  • Figs. 3 to 6 are transmission electron microscope photographs showing crystal growth when an amorphous silicon thin film in about 500 nm thick is doped with an impurity such as P (phosphorus) in an average concentration of c.a. 4 ⁇ 10 20 /cm 3 at near the interface of the underlying film, followed by heat treatment for polycrystallization.
  • Figs. 3 to 6 are transmission electron microscope photographs showing crystal growth when an amorphous silicon thin film in about 500 nm thick is doped with an impurity such as P (phosphorus) in an average concentration of c.a. 4 ⁇ 10 20 /c
  • FIG. 3 and 5 are cross-sectional views of the thin film, and Figs. 4 and 6 are surface views of the thin film. Further, Figs. 5 and 6 show the case of forming a non-doped layer.
  • Fig. 7 is a flow chart showing a process for producing a gate electrode film.
  • step (i) deposition of a P-doped silicon thin film begins.
  • a raw material gas e.g. SiH 4 gas or Si 2 H 6 gas
  • a P doping gas e.g. PH 3 gas
  • the deposition of P-doped amorphous silicon film 4 is continued to a predetermined thickness (v).
  • the total thickness and average P concentration of the thin film are made equal to the case of not positively controlling the P concentration near the interface of underlying film.
  • the amorphous silicon thin film shown in Fig. 1 is formed (vi).
  • P-doped polycrystalline silicon film 5 is formed by crystallization.
  • the thus polycrystallized film is obtained by initially growing individual crystal grains from near the interface of underlying film and further growing columnar structure to the thin film surface.
  • Figs. 3 and 5 observed from the cross-sectional direction.
  • the crystal nucleuses of individual crystal grains are generated near the interface of underlying film.
  • the plane shape of crystal grains is divided into two kinds as shown in Fig. 4 when the non-doped layer is not formed. That is, there are crystal grains grown in the asteroid shape and crystal grains grown in the elliptic shape in admixture.
  • crystal grains having the asteroid shape are not admitted and only crystal grains having the elliptic shape are admitted.
  • the elliptic crystals have the (311) crystal plane grown to the thin film surface. This is confirmed by the measured results by electron diffractometry.
  • the thickness of the layer not doped with the impurity is as small as possible so as to make the crystal growth mode uniform and the amount of impurity for doping in the upper layer of the thin film is a sufficient amount for controlling the electric resistance as a whole to a predetermined value.
  • the thickness of 10 nm or less is sufficient to show the above-mentioned effect.
  • the thickness of the layer not containing the impurity is preferably 1 to 10 nm.
  • the predetermined time for depositing the amorphous film means a time necessary for depositing the film having the film thickness in the above-mentioned range.
  • the crystal growth can be controlled by controlling the P concentration at the beginning of the film deposition.
  • the (311) crystal plane grows predominantly by making a time lag of introduction of P, while the (211) crystal plane grows predominantly when P is introduced positively.
  • the thin film having the above-mentioned structure can be formed without divided two steps.
  • the flow of a dopant gas can be started after a predetermined time from the beginning of flow of a raw material gas for forming the silicon thin film.
  • the impurity used as a dopant is not limited to P, and B (boron) or As (arsenic) can also be used. Therefore, the dopant gas, the doped amorphous silicon film and the polycrystalline silicon thin film can include B or As in place of P. This can also be applied to the Examples mentioned below.
  • the crystallization is conducted after patterning of amorphous silicon film (after the state shown by Fig. 1), but not limited thereto and possible before the patterning. Further, as the impurity, B or As can be used as a dopant in place of P. This can also be applied to the Examples mentioned below.
  • the process of this Example is not limited to the production of the gate electrode of the MOS transistor structure, and can be applied to the production of an emitter electrode, a base electrode and a collector electrode of bipolar transistors, or a gate electrode, a floating electrode, and a control electrode of flash memory structure.
  • This Example is explained referring to Figs. 7, 8 and 9.
  • the present invention is applied to the formation of polycrystalline silicon thin film forming a semiconductor device such as transistors and diodes.
  • Fig. 7 is a flow chart showing the steps for forming the polycrystalline silicon thin film.
  • Fig. 8 is a cross-sectional view showing the state immediately after the deposition of the thin film
  • Fig. 9 is a cross-sectional view of the transistor formed in the polycrystalline silicon thin film, wherein numeral 8 denotes an underlying film, numeral 9 denotes an emitter electrode, numeral 10 denotes a base electrode, numeral 11 is a collector electrode, and numeral 12 is a substrate.
  • numeral 8 denotes an underlying film
  • numeral 9 denotes an emitter electrode
  • numeral 10 denotes a base electrode
  • numeral 11 is a collector electrode
  • numeral 12 is a substrate.
  • the step of introduction of impurity for forming the transistor is omitted, since it has no direct relation to the essence of this Example.
  • an underlying film 8 made from a different material (e.g. SiN) from silicon is formed on a silicon substrate 1.
  • a P-doped silicon thin film is formed (i).
  • the raw material gas e.g. SiH 4 gas or Si 2 H 6 gas
  • a non-doped amorphous silicon layer 3 having the predetermined thickness is formed (iii).
  • an impurity of P as a dopant gas is introduced (iv).
  • the deposition of P-doped amorphous silicon film 4 is continued to obtain the predetermined thickness (v).
  • the thickness of the whole thin film and the average P concentration therein are made equal to the case of not positively controlling the P concentration near the interface of underlying film.
  • Fig. 8 is a cross-sectional view of the thus produced thin film (vi).
  • the base electrode 10, the emitter electrode 9, the collector electrode 11, etc. are formed. These electrodes are not always be required to be formed nearby, and the order of the positions of them can be optional. Further, the transistor formed in the polycrystalline silicon thin film is not always limited to the bipolar transistor, and it can be a diode, or other type of transistor, and the like semiconductor device.
  • the non-doped layer is present near the interface of underlying film under the P-doped amorphous silicon thin film, there can be obtained a polycrystalline layer having the orientation predominantly (90% or more) in the direction of the (311) crystal plane or (211) crystal plane. Further, since the P-doped silicon thin film stable in internal stress can be obtained, properties of the semiconductor device (e.g. transistor) formed in individual crystal grains are low in variation, and thus remarkably stabilized.
  • the semiconductor device e.g. transistor
  • Fig. 10 is a cross-sectional view of a gate electrode in a MOS transistor obtained from the polycrystalline silicon thin film deposited according to the present invention.
  • a P-doped silicon thin film is deposited using a SiH 4 gas on a silicon oxide film 2 formed on a silicon substrate 1 (i).
  • SiH 4 gas raw material gas
  • a non-doped amorphous silicon layer 3 having a predetermined thickness is formed.
  • the film having an orientation in the (311) crystal plane direction is formed (iii).
  • a dopant P gas is introduced (iv).
  • a P-doped amorphous silicon film 4 is deposited continuously to obtain a predetermined thickness (v).
  • the thickness of whole thin film and P concentration therein are made equal to the case of not positively controlling the P concentration near the interface of underlying film (vi).
  • the heat treatment for crystallization is carried out to form the P-doped polycrystalline silicon film 5.
  • the polycrystalline layer having the structure shown in Fig. 10.
  • Fig. 11 is a cross-sectional view of a flash memory, wherein numeral 27 denotes a floating electrode, and numeral 28 denotes a polycrystalline silicon thermal oxidation film.
  • the flash memory comprises a silicon substrate 1, a silicon oxide film 2 (a ultrathin oxidized film) formed thereon, a P-doped polycrystalline silicon film 5 formed on the silicon oxide film, a polycrystalline silicon thermal oxidation film 28 formed by thermal oxidation of the surface of the polycrystalline silicon thin film, and an electroconductive thin film 27 which is to become a floating electrode formed on the polycrystalline silicon thermal oxidation film 28.
  • the P-doped polycrystalline silicon film 5 can be produced either by producing the non-doped layer near the interface of underlying oxide film as described in Example 1.
  • the resulting P-doped polycrystalline silicon film has an orientation in an almost uniform direction as explained previously.
  • the thickness of the thermal oxidation film grown on individual grains becomes uniform. This is a result of losing an influence of the anisotropy wherein the growth speed of oxidation film is different in crystal plane directions, in the case of thermal oxidation of silicon crystals. Thus, it is possible to obtain the uniform film thickness.
  • thermal oxidation film 28 is formed between the P-doped polycrystalline silicon film 5 and the floating electrode 27, but in order to enhance a dielectric constant, it is possible to form a silicon nitride film or a laminate of a silicon nitride film and a silicon oxide film between the thermal oxidation film 28 and the floating electrode 27. It is also possible to use B or As as a dopant in place of P.
  • the film thickness of the thermal oxidation film can be formed uniformly locally (in the unit of each crystal grain) between the P-doped polycrystalline silicon film 5 and the floating electrode 28, it is possible to control the variation of pressure resistance caused by variation in the oxidation film thickness and to design the thickness of the oxidation film as thin as possible.
  • FIG. 12 is a schematic view of a chemical vapor deposition (CVD) apparatus, wherein numeral 20 denotes a reaction chamber for depositing the thin film, numeral 21 denotes a gas introducing unit, numeral 22 denotes a gas flow control valve, numeral 23 denotes a gas bomb for depositing a silicon thin film, numeral 24 denotes a gas bomb for introducing an impurity element, numeral 25 denotes a film deposition control unit in the reaction chamber, numeral 26 denotes a gas exhaust unit, numeral 31 is a wafer and numeral 32 is a board.
  • an upright type CVD apparatus is shown (a heater is not shown in the drawing), but it is possible to use a lateral type CVD apparatus or a sheet treating type.
  • the film deposition control unit 25 is to control the temperature in the reaction chamber, and to control transport of a substrate on which the thin film is to be deposited.
  • the gas bomb 23 is used for storing the raw material gas (e.g. SiH 4 gas or Si 2 H 6 gas) for depositing the silicon thin film.
  • the gas bomb 24 is used for storing the impurity gas as a dopant such as P, B, As, etc.
  • the gas introducing unit 21 controls the timing of introducing each gas into the reaction chamber 20 and the timing of opening or closing the gas flow control valve 22 for depositing the P-doped silicon thin film according to the process shown in Fig. 7.
  • each one path for introducing the raw material gas and the impurity gas is shown, but it is possible to use a plurality of pipes for introducing these gases into the reaction chamber 20. In either case, the gas introduction paths and gas introduction timing should be controlled by the gas introducing unit 21.
  • the impurity-doped silicon thin film can be either an amorphous silicon layer or a polycrystalline silicon layer.
  • crystal orientation of (311) plane, (211) plane or (111) plane is illustrated but not limited thereto.
  • the crystal plane can also include the (100) plane, (110) plane, and the like.
  • the polycrystalline silicon thin film and the semiconductor device using the silicon thin crystal can be controlled to have an almost uniform crystal plane direction, thus the homogeneous polycrystalline silicon thin film having a stabilized internal stress value can be produced stably in a high yield.

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Claims (9)

  1. Verfahren zur Herstellung einer Dünnschichtelektrode (5) aus polykristallinem Silizium, das mit einer Verunreinigung, ausgewählt aus Elementen der Gruppen III oder V dotiert ist, auf einer darunter liegenden Schicht (2) eines Substrats (1) eines Halbleiterbauteils, wobei eine reine amorphe Siliziumschicht (3) auf der darunter liegenden Schicht (2) abgeschieden wird und die Konzentration und die Verteilung der Verunreinigung in der Nähe der Grenzfläche (30) zwischen der reinen amorphen Siliziumschicht (3) und der darunter liegenden Schicht (2) gesteuert wird durch
    Abscheiden der reinen amorphen Siliziumschicht (3) aus reinem SH4-Gas und/oder S2H6-Gas auf der darunter liegenden Schicht (2) bis zu einer Dicke von 1 - 10 nm,
    Abscheiden einer amorphen, in-situ dotierten Siliziumschicht (4) aus einer Gasmischung aus SH4-Gas und/oder S2H6-Gas auf der amorphen reinen Siliziumschicht, wobei ein Gas das Dotierungselement (3) enthält, und wobei die resultierende amorphe Schicht (4) eine Dotierungselementkonzentration aufweist, die ausreichend ist, um für einen geringen Widerstand der polykristallinen Dünnschichtelektrode (5) zu sorgen, und
    Wärmebehandeln zur Kristallisation der abgeschiedenen amorphen Schichten (3, 4), so dass die Siliziumkörner der polykristallinen Siliziumdünnschicht (5) von der Grenzfläche (30) zur Oberfläche der Dünnschichtelektrode (5) in einer im wesentlichen säulenförmigen Struktur wachsen mit einer gleichmäßigen Orientierung von mindestens 60 % der Kristalle der resultierenden Dünnschicht (5), die in der gleichen Richtung orientiert sind.
  2. Verfahren nach Anspruch 1, dadurch gekennzeichnet, dass die Kristalle der polykristallinen Siliziumschicht (5) wachsen, wobei die (211)- oder die (311)-Kristallebene in der Oberfläche der Dünnschicht (5) orientiert ist.
  3. Verfahren nach einem der Ansprüche 1 oder 2, dadurch gekennzeichnet, dass das Abscheiden der amorphen Schichten (3, 4) aus der Gasphase bei einer Temperatur von 500 bis 600 °C durchgeführt wird.
  4. Verfahren nach einem der Ansprüche 1 bis 3, dadurch gekennzeichnet, dass die Polykristallisations-Wärmebehandelung der amorphen Schichten (3, 4) bei einer Temperatur von 550 bis 1000 °C durchgeführt wird.
  5. Verfahren nach einem der Ansprüche 1 bis 4, dadurch gekennzeichnet, dass das Aufbringen einer Gate-Elektrode nach der Bildung der zweiten Siliziumschicht (4) und vor der Wärmebehandlung durchgeführt wird.
  6. Verfahren nach einem der Ansprüche 1 bis 5, dadurch gekennzeichnet, dass das Dotierungselement Phosphor, Bor, Arsen oder eine Mischung davon ist.
  7. Verfahren nach einem der Ansprüche 1 bis 6, dadurch gekennzeichnet, dass die zweite amorphe Siliziumschicht (4) nach einer vorbestimmten Zeit nach dem Zuführen von reinem Si-Gas zur Bildung der ersten amorphen Siliziumschicht (3) gebildet wird.
  8. Verfahren nach einem der Ansprüche 1 bis 7, dadurch gekennzeichnet, dass die zweite amorphe Siliziumschicht aus einem Gas mit SiH2- oder Si2H6-Material abgeschieden wird, das PH3 enthält.
  9. Verfahren nach einem der Ansprüche 1 bis 8, dadurch gekennzeichnet, dass das Halbleiterbauteil ein Metalloxidhalbleiter(metal-oxide-semidconductor, MOS)-Transistor ist.
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EP0707344A3 (de) 1996-08-28
TW475252B (en) 2002-02-01
KR960012313A (ko) 1996-04-20
KR100396400B1 (ko) 2003-09-03
US5670793A (en) 1997-09-23
EP0707344A2 (de) 1996-04-17
JPH0888173A (ja) 1996-04-02
KR100270192B1 (ko) 2000-12-01
US6080611A (en) 2000-06-27
EP1209726A3 (de) 2002-10-09
KR100397086B1 (ko) 2003-09-06
DE69527827T2 (de) 2003-04-03
US6559037B2 (en) 2003-05-06
JP3599290B2 (ja) 2004-12-08
CN1128898A (zh) 1996-08-14
EP1209726A2 (de) 2002-05-29
US6204155B1 (en) 2001-03-20
CN1054235C (zh) 2000-07-05
TW541684B (en) 2003-07-11
US20020013038A1 (en) 2002-01-31
DE69527827D1 (de) 2002-09-26
US6187100B1 (en) 2001-02-13

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