EP0710426A1 - Convertisseur de debit binaire en serie pour matrice de commutation a multiplexage temporel - Google Patents

Convertisseur de debit binaire en serie pour matrice de commutation a multiplexage temporel

Info

Publication number
EP0710426A1
EP0710426A1 EP94921555A EP94921555A EP0710426A1 EP 0710426 A1 EP0710426 A1 EP 0710426A1 EP 94921555 A EP94921555 A EP 94921555A EP 94921555 A EP94921555 A EP 94921555A EP 0710426 A1 EP0710426 A1 EP 0710426A1
Authority
EP
European Patent Office
Prior art keywords
serial
input
parallel
time division
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP94921555A
Other languages
German (de)
English (en)
Other versions
EP0710426B1 (fr
Inventor
Simon Skierszkan
Jim Lehmann
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Microsemi Semiconductor ULC
Original Assignee
Mitel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitel Corp filed Critical Mitel Corp
Publication of EP0710426A1 publication Critical patent/EP0710426A1/fr
Application granted granted Critical
Publication of EP0710426B1 publication Critical patent/EP0710426B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/04—Distributors combined with modulators or demodulators
    • H04J3/047—Distributors with transistors or integrated circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/08—Time only switching

Definitions

  • This invention relates to a time division switching matrix capable of effecting rate conversion.
  • PCM pulse coded modulation
  • a time division switching matrix capable of effecting rate conversion comprising a plurality of serial inputs for connection to respective serial input links, each capable of carrying time division multiplexed PCM channels, a plurality of serial outputs for connection to respective serial output links, each capable of carrying time division multiplexed PCM channels, and a serial-to- parallel converter associated with each input for converting a serial input stream to parallel format, each said serial-to-parallel converter being independently configurable to produce the same net parallel throughput regardless of the bit rate of the associated input link.
  • the invention allows for rate conversion in the switching matrix, for example, between PCM highways of 2.048 megabits per second, and 4.096 megabits per second, or 2.048 megabits per second and 8.192 megabits per second. It also allows for conversion from 8.192 megabits per second to 2.048 megabits per second, or 4.096 megabits per second and 2.048 megabits per second. With rate conversion, networks with differing serial backplanes can be interconnected.
  • the switching core of the device consists of a ram based time switch that switches 256 x 256 channel locations.
  • 256 bytes of incoming PCM data are written in sequence into a data ram.
  • 256 reads of the same memory fetch PCM data bytes, which are shifted out onto serial output links. The time at which the fetch occurs determines the output link and channel number that the PCM data is to be routed to.
  • Figure 1 is a diagram showing the memory address timing for a switching matrix in accordance with the invention
  • Figure 2 is a diagram showing the inputs shift registers for the 2Mb/s mode
  • FIG. 3 shows the input data stream redirects for the 4Mb/s mode
  • Figure 4 shows the input data stream redirects for 8Mb/s mode
  • FIG. 5 shows the 2Mb/s configuration
  • Figure 6 shows the output data stream redirects for the 4Mb/s mode
  • FIG. 7 shows the 8Mb/s timing
  • Figure 8 shows the output data stream redirects for the 8Mb/s mode
  • FIG. 9 is a block diagram of a switching matrix in accordance with the invention.
  • the switching matrix shown in Figure 9 comprises input Mux 1, 2 each containing reconfigurable shift registers and producing 8 bit parallel output on input buses 3, 4, 5, 6 connected directly to memories 7, 8, 11, 12, and through Mux 16 to memories 9,10.
  • the memories are in turn are connected to parallel output buses 13.
  • Output buses 13 are connected through data select switch 14 to output Mux 15, which is connected to eight serial output links.
  • the switch also includes a counter 17, a frame counter 18, an address control unit 19, and low and high memories 20, 21.
  • the switching matrix can switch between 8 physical input links with 32 time multiplexed PCM channels and 8 output links with 32 channels. As the speed of the input (output) data rate is increased, the number of input
  • the switching memory always operates with a nominal 244 nanosecond cycle time.
  • Data memory writes are doubled up, i.e. 2 PCM bytes from the serial input are written in parallel to free up clock cycles for time multiplexed memory accesses.
  • incoming serial data is converted into a parallel format in sequence, to allow for 128 writes, of two bytes each, to be performed. This is accomplished by providing input shift registers that can be reconfigured to produce the same net parallel throughput independently of the serial bit rate of the input links.
  • serial input links available for input at 2.048 megabits per second operation. At 4.096 megabits per second only the first 4 are used, and at 8.192 megabits per second, only the first 2 are used. Blocking modes are also available that allow the use of more inputs.
  • the base input configuration, as used in the 2.048 megabit per second input data rate is shown in Figure 2, which shows serial inputs streams STIO - STI7 input through redirect circuit 40 to a staggered length set of input shift registers 31 - 38. These are followed by a set of 8 tristateable latches with parallel data taps 31a - 38a.
  • the time at which the input data is ready to be parallel loaded can bee effectively delayed, (i.e. when the output latches are enabled) in turn, from each latch set.
  • the timing of this scheme is such that input stream 0&4 are written to data memory first, followed in sequence by 1 &5, 2&6 and 3&7, all in two 8 bit byte parallel format.
  • the circuit With input data at 4 megabits per second, the circuit operates without changing the base set of input registers seen in Figure 2, and within the constraints of the internal data memory write and read cycle timing as shown in Figure 1. This is accomplished by redirecting the input streams to new sets of input latches, with the proper number of delay registers to align them with the internal enable / write timing pulses. This redirection for the 4 megabits per second mode is shown in Figure 3.
  • the input sftm STIO continues into the first set of latches, while the input stream STI1 is redirected down one set, the input stream STI2 is redirected down two sets, and the input stream STI3 is redirected down three sets.
  • This allows the data memory write cycles to remain in the same spot in the overall timing scheme, with only a minor modification to the coding of the input load pulses themselves. Instead of loading in an ascending pair sequence, the data is loaded from input latch sets 0&4, and then from 2&6 in a repeating sequence.
  • the output latch sets undergo a similar mapping strategy to accommodate the variable output rates in both standard and rate conversion modes.
  • the output loads also base their timing on the internal data memory timing cycle seen in Figure 1, with 8 output register loads in one internal channel. These occur during the period labeled "data memory internal read accesses" in Figure 1. With 32 internal channels in one frame, and 8 output loads per channel, the desired 256 bytes of output data are achieved in one 125 microsecond frame.
  • the base 2 megabit per second output configuration is seen in Figure 5.
  • the output register sets consist of 8 bit loadable shift registers 51 - 58 followed by a variable length set of buffer registers. The variable length buffer registers play no part in the base 2 megabits per second mode.
  • the data is effectively loaded directly in to the "load & delay" section 51 - 58 and streams out with no additional delay.
  • the staggered set of output registers are necessary to ensure that the data for each output stream aligns properly with the data stream channel boundary.
  • the output of registers 61-68 passes to output redirect circuit 70, where it emerges as 8 serial output streams STOO-STO-7.
  • the load sequence is 0,2,4,6,0,2,4,6. This accommodates the 4 megabits per second output data rate while allowing the internal memory access and shift register load pulse timing to remain unchanged.
  • Figure 8 For an 8 megabits per second output mode ( Figure 8) , a similar reconfiguration occurs.
  • the output streams must be delayed by the appropriate number of additional cycles to align with the channel boundary. This is achieved by loading output latch sets 1 and 5, and redirecting the resulting data streams.
  • the output load sequence in one internal channel is 1,5,1,5,1,5,1,5. This allows the 8 megabits per second data rate on the two output streams to be met within the constraints of the internal timing cycle.
  • the architecture of the design allows for independence between the input and output modes.
  • the input write addressing is based solely on the internal timing, with a variable addressing structure converting the connect memory contents to the appropriate address for output data reads.
  • the connect memory addressing is dependent only on the output mode, and is automatically adjusted to compensate for the selected output mode.
  • the input and output modes are essentially independent, and so are easily reconfigurable around the internal timing, to make backplane as well as rate conversion modes possible.
  • the architecture is also easily extensible, with the simple addition of a new input and output mode decoding, and a slight modification to the load timing circuitry.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)

Abstract

Une matrice de commutation à répartition dans le temps capable d'effectuer une conversion de débit comprend une pluralité d'entrées en série permettant la connexion à des liaisons respectives d'entrée en série, chacune étant capable d'acheminer le trafic de canaux MIC multiplexés par répartition dans le temps, une pluralité de sorties en série permettant la connexion à des liaisons respectives de sortie en série, chacune étant capable d'acheminer le trafic de canaux MIC multiplexés par répartition dans le temps, et un convertisseur série-parallèle associé à chaque entrée et convertissant un courant d'entrée en série en une structure parallèle, chacun de ces convertisseurs série-parallèle étant configurable indépendamment afin de produire le même débit parallèle net quel que soit le débit binaire de la liaison d'entrée associée. Le côté sortie de la matrice de commutation peut être configuré de manière similaire.
EP94921555A 1993-07-16 1994-07-13 Convertisseur de debit binaire en serie pour matrice de commutation a multiplexage temporel Expired - Lifetime EP0710426B1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
CA002100729A CA2100729C (fr) 1993-07-16 1993-07-16 Convertisseur de debit binaire serie incorpore a une matrice de commutation
CA2100729 1993-07-16
PCT/CA1994/000377 WO1995002951A1 (fr) 1993-07-16 1994-07-13 Convertisseur de debit binaire en serie pour matrice de commutation a multiplexage temporel

Publications (2)

Publication Number Publication Date
EP0710426A1 true EP0710426A1 (fr) 1996-05-08
EP0710426B1 EP0710426B1 (fr) 1997-10-01

Family

ID=4151939

Family Applications (1)

Application Number Title Priority Date Filing Date
EP94921555A Expired - Lifetime EP0710426B1 (fr) 1993-07-16 1994-07-13 Convertisseur de debit binaire en serie pour matrice de commutation a multiplexage temporel

Country Status (6)

Country Link
US (1) US5818834A (fr)
EP (1) EP0710426B1 (fr)
JP (1) JPH09502579A (fr)
CA (1) CA2100729C (fr)
DE (1) DE69406008T2 (fr)
WO (1) WO1995002951A1 (fr)

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GB9509831D0 (en) 1995-05-15 1995-07-05 Gerzon Michael A Lossless coding method for waveform data
KR100204918B1 (ko) * 1997-05-23 1999-06-15 윤종용 워드 오퍼레이션을 수행하는 제어메모리를 갖춘 타임스위치 및 이의 제어방법
EP0961435A3 (fr) * 1998-05-26 2003-09-17 Siemens Information and Communication Networks Inc. Méthode et système d'accès à une mémoire tampon parallèle à l'aide de données série
SE518865C2 (sv) 1998-12-22 2002-12-03 Switchcore Ab Anordning och metod för omvandling av data i seriellt format till parallellt format och vice versa
US7039074B1 (en) 2000-09-14 2006-05-02 Agiletv Corporation N-way demultiplexer
US7047196B2 (en) 2000-06-08 2006-05-16 Agiletv Corporation System and method of voice recognition near a wireline node of a network supporting cable television and/or video delivery
US8095370B2 (en) 2001-02-16 2012-01-10 Agiletv Corporation Dual compression voice recordation non-repudiation system
GB0118196D0 (en) * 2001-07-26 2001-09-19 Zarlink Semiconductor Ltd Apparatus for switching time division multiplex channels
JP4594930B2 (ja) * 2003-06-03 2010-12-08 スターレント・ネットワークス・エルエルシー データを再フォーマットするためのシステムおよび方法
TWI263934B (en) * 2003-09-19 2006-10-11 Via Tech Inc Synchronous periodical orthogonal data converter
JP4437480B2 (ja) * 2006-08-03 2010-03-24 富士通株式会社 パケット伝送装置及びその制御方法
CN101207471B (zh) * 2007-12-12 2011-09-21 上海华为技术有限公司 对时隙进行交换的方法与装置

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FR2265240B1 (fr) * 1974-03-22 1977-09-30 Constr Telephoniques
FR2376572A1 (fr) * 1976-12-30 1978-07-28 Roche Alain Circuits de conversion serie-parallele et de multiplexage ou de conversion parallele-serie et de demultiplexage pour des multiplex numeriques
US5060227A (en) * 1988-02-29 1991-10-22 Motorola, Inc. Digital telephone switch with simultaneous dual PCM format compatibility
CA2001100A1 (fr) * 1988-10-31 1990-04-30 Anthony Jessop Reseaux de transmission
US5359605A (en) * 1989-06-22 1994-10-25 U.S. Philips Corporation Circuit arrangement for adjusting the bit rates of two signals
US5119368A (en) * 1990-04-10 1992-06-02 At&T Bell Laboratories High-speed time-division switching system
DE4117869A1 (de) * 1991-05-31 1992-12-03 Standard Elektrik Lorenz Ag Raum- und zeit-koppelelement
US5337181A (en) * 1992-08-27 1994-08-09 Kelly Shawn L Optical spatial filter
US5471466A (en) * 1993-11-17 1995-11-28 Gte Laboratories Incorporated Method and apparatus for ATM cell alignment

Non-Patent Citations (1)

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See references of WO9502951A1 *

Also Published As

Publication number Publication date
DE69406008T2 (de) 1998-04-16
DE69406008D1 (de) 1997-11-06
CA2100729A1 (fr) 1995-01-17
JPH09502579A (ja) 1997-03-11
CA2100729C (fr) 2001-01-16
US5818834A (en) 1998-10-06
EP0710426B1 (fr) 1997-10-01
WO1995002951A1 (fr) 1995-01-26

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