EP0744848A1 - Synchronisation d'un détecteur Viterbi avec rétroaction vers l'échantillonneur - Google Patents

Synchronisation d'un détecteur Viterbi avec rétroaction vers l'échantillonneur Download PDF

Info

Publication number
EP0744848A1
EP0744848A1 EP96107157A EP96107157A EP0744848A1 EP 0744848 A1 EP0744848 A1 EP 0744848A1 EP 96107157 A EP96107157 A EP 96107157A EP 96107157 A EP96107157 A EP 96107157A EP 0744848 A1 EP0744848 A1 EP 0744848A1
Authority
EP
European Patent Office
Prior art keywords
viterbi detector
signal processing
processing system
phase
sampling
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP96107157A
Other languages
German (de)
English (en)
Other versions
EP0744848B1 (fr
Inventor
Jürgen Kaaden
Gerhard Reiner
Dietmar Bräuer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Deutsche Thomson Brandt GmbH
Original Assignee
Deutsche Thomson Brandt GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Deutsche Thomson Brandt GmbH filed Critical Deutsche Thomson Brandt GmbH
Publication of EP0744848A1 publication Critical patent/EP0744848A1/fr
Application granted granted Critical
Publication of EP0744848B1 publication Critical patent/EP0744848B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
    • H04L7/0062—Detection of the synchronisation error by features other than the received signal transition detection of error based on data decision error, e.g. Mueller type detection
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • G11B20/10037—A/D conversion, D/A conversion, sampling, slicing and digital quantisation or adjusting parameters thereof
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • G11B20/10222—Improvement or modification of read or write signals clock-related aspects, e.g. phase or frequency adjustment or bit synchronisation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • G11B20/10305—Improvement or modification of read or write signals signal quality assessment
    • G11B20/10398—Improvement or modification of read or write signals signal quality assessment jitter, timing deviations or phase and frequency errors
    • G11B20/10425—Improvement or modification of read or write signals signal quality assessment jitter, timing deviations or phase and frequency errors by counting out-of-lock events of a PLL
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/33—Synchronisation based on error coding or decoding
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0334—Processing of samples having at least three levels, e.g. soft decisions
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B2220/00—Record carriers by type
    • G11B2220/20—Disc-shaped record carriers
    • G11B2220/25—Disc-shaped record carriers characterised in that the disc is based on a specific recording technology
    • G11B2220/2508—Magnetic discs
    • G11B2220/2516—Hard disks
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B2220/00—Record carriers by type
    • G11B2220/20—Disc-shaped record carriers
    • G11B2220/25—Disc-shaped record carriers characterised in that the disc is based on a specific recording technology
    • G11B2220/2537—Optical discs
    • G11B2220/2562—DVDs [digital versatile discs]; Digital video discs; MMCDs; HDCDs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B2220/00—Record carriers by type
    • G11B2220/90—Tape-like record carriers

Definitions

  • the invention is based on a signal processing system for digital signals according to the preamble of claim 1.
  • PLL Phase Locked Loop
  • decision-makers are provided for converting the digital data from the analog sampled signals, which, in the case of the new systems such as DVC (tape recording) or DVD (optical playback), are designed as a Viterbi detector in a self-adapting form that is optimally adapted to the storage medium type.
  • the Viterbi detector usually works digitally, i.e. the analog signal is digitized using an A / D (analog / digital) converter and fed to the detector.
  • sampling time is influenced by the behavior of the PLL and the equalization. It is also dependent on the distortions that have arisen during recording and on the thermal behavior of the electronics. In reality, a variance of around 10% can be expected.
  • a non-optimal, "eye-centered" sampling time leads to increased wrong decisions in the Viterbi detector, which it automatically corrects to a certain extent. The error correction will usually correct the rest of the remainder, whereby in the event of additional drops in amplitude due to tape scratches or defects in the tape, the correction capacity can be exceeded quickly. The result is data loss.
  • the invention has for its object to improve the sampling time of the overall system. This object is achieved by the features of the invention specified in claim 1. Advantageous developments of the invention are specified in the subclaims.
  • the Viterbi detector present in the system is expanded by a control output, which controls a variable delay line at the output or within the PLL.
  • Signal processing system for digital signals consisting of a clock recovery stage, a clocked sampling stage and a Viterbi detector as a decision stage.
  • the phase of the scan is shifted by the control output of the Viterbi detector so that the scan position in the Eye opening position is carried out, which corresponds to the minimum error rate.
  • the error rate information is obtained from the sum of the incorrect decisions determined and corrected in the Viterbi detector per unit of time.
  • the optimization is started automatically when a predetermined high error value is exceeded and automatically ended when the value falls below a predetermined low error value, the output value determined last being retained and the optimization being activated continuously.
  • the system is started with an average value or the system starts with the last determined, saved output value.
  • the Viterbi detector which has control outputs, changes the clock phase at the input of the sampling stage.
  • the phase of the clock recovery is directly changed by feeding a phase offset, which is controlled by the Viterbi detector output via a digital / analog converter.
  • the sampling stage contains an analog / digital converter.
  • the optimization process is constructed iteratively by evaluating each faulty level transition by evaluating the error result after switching on a changed scanning position and starting the corresponding next action.
  • Areas of application are advantageously used for all systems that have a PLL for data synchronization, digital signal sampling and a Viterbi detector.
  • Receivers for digital transmission systems DVD, DSS, ATV ..
  • Playback electronics of optical storage systems HDCD, DVD
  • Playback electronics of magnetic storage systems helical track recording
  • DVC-digital video cassette helical track recording
  • SDCR-stationary digital cassette recorder Data recording
  • n 1 shows an incorrect decoding of the DVC data signal.
  • the sampling times n, n + 1 and n + 2 are shown on the time axis T and the analog / digital converter values A / D with the marked points x-high, high level and x-mean.
  • the curve shape K is also shown.
  • the representation relates to a ternary signal scheme in which edge changes are represented as +1 or -1 and the mean level has the value 0.
  • the curve represents a +1 signal jump, any noise components are hidden.
  • xmean represents the average level value that occurs between edge changes and corresponds to the value 0.
  • the high-level area marks above which a pulse is recognized as +1.
  • the mean value xhigh represents the +1 level. (Consequently, the value limits low-level and xlow exist for evaluating the -1 signal jumps). Given the precoding of both recordings, only a maximum of 2 consecutive +1 or -1 values are permitted. In the specific case shown, after checking the level relationships, the Viterbi detector will conclude that there is a faulty pulse at time n + 2. At the same time this error is assigned to the falling edge to enable clear control direction detection.
  • Fig. 2 shows the playback head 1, the playback amplifier 2, a component unit 3 and the Viterbi detector 4 with the outputs clock and data.
  • the component unit 3 consists of an equalizer 5 of a PLL circuit PLL, a phase shifter 6 and an A / D converter 7.
  • the playback head reads the signal from the tape, which is brought to a level of several 100 mV in the subsequent playback amplifier.
  • the equalizer compensates for higher frequency level losses and includes a group delay correction.
  • Signals according to FIG. 1 are available at its output.
  • the PLL circuit is controlled by signal edge changes, the times of which are compared and synchronized with the edge changes of a voltage-controlled oscillator (not shown).
  • a delay line that can be switched in ns steps is connected to the output of the PLL. Its output feeds the clock input of an A / D converter, at whose input the signal coming from the equalizer is present.
  • the output signals from the converter are fed to the Viterbi detector. This in turn provides the correction value for the clock delay at one output, and the decided data signal, which is synchronized to the clock, is available at a further output.
  • FIG. 3 shows an image of an oscillograph with the optimal sampling times.
  • the illustration shows the output signal of the equalizer measured continuously over a longer period of time. This is the eye diagram of a ternary signal. For minimum error rate, scanning must be done at the time of maximum eye opening.
  • FIG. 4 shows the Viterbi detector 4. It receives a clock signal clk from the PLL circuit PLL and the converted signal of the equalizer 5, not shown here, from the A / D converter 7.
  • the signal from the A / D converter 7 is passed on to the decision maker 8 and the peak value detector 9.
  • decision maker 8 the decision for +1; Hit -1 and 0.
  • the two outputs are fed to 2 monitoring shift registers in module 10.
  • the peak detector 9 measures the levels and marks the transitions with the least probability (for example at the time n + 2 in FIG. 1) after +1 and -1 transitions separately. These marker bits are fed to the monitoring shift registers in the assembly 10 which are separate from the decision bits.
  • the comparator 12 are the illegal transitions +1 >> 0 >> + 1; -1 >> 0 >> - 1; +1 >> - 1 >> + 1; -1 >> + 1 >> - 1 detected and corrected, the content of the data monitoring register being changed.
  • the counter 11 determines the number of consecutive +1 or -1 levels. A value> 2 indicates, according to the pre-coding, an error.
  • the assemblies 13-17 show the solution according to the invention for the corrections associated with the respective edge changes for an iterative process.
  • the edge correction counter 15 which is composed of the correction counter 13 for left edges and correction counter 14 for right edges, counts the corrections that occur per unit of time (e.g. number of clock cycles).
  • the comparator 16 determines the correction device and starts or ends the process by counting the absolute corrections.
  • the output signal is provided in assembly 17 and the edge count is reset after the output.
  • Both units pass the evaluated signal to a monitoring shift register 10.
  • the monitoring shift register 10 is connected to the counter 11 and the comparator 12.
  • the counter 11 outputs its evaluation to the left flank 13 and Comparator 12 continues its evaluation on the right flank 14.
  • the left edge 13 and the right edge 14 contain an edge correction counter 15 and these three units are combined in a next comparator 16.
  • the comparator 16 is connected to the phase shifter 17, which in each case passes on a reset signal.
  • the phase shifter controller 17 has a left and right phase shifter 18, 19 as an output.

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Error Detection And Correction (AREA)
  • Television Signal Processing For Recording (AREA)
EP96107157A 1995-05-16 1996-05-07 Synchronisation d'un détecteur Viterbi avec rétroaction vers l'échantillonneur Expired - Lifetime EP0744848B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19517405A DE19517405A1 (de) 1995-05-16 1995-05-16 Signalverarbeitungssystem für digitale Signale
DE19517405 1995-05-16

Publications (2)

Publication Number Publication Date
EP0744848A1 true EP0744848A1 (fr) 1996-11-27
EP0744848B1 EP0744848B1 (fr) 2002-04-03

Family

ID=7761718

Family Applications (1)

Application Number Title Priority Date Filing Date
EP96107157A Expired - Lifetime EP0744848B1 (fr) 1995-05-16 1996-05-07 Synchronisation d'un détecteur Viterbi avec rétroaction vers l'échantillonneur

Country Status (6)

Country Link
US (1) US5940449A (fr)
EP (1) EP0744848B1 (fr)
JP (1) JPH08315518A (fr)
DE (2) DE19517405A1 (fr)
ES (1) ES2174994T3 (fr)
MY (1) MY113906A (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998049811A3 (fr) * 1997-04-25 1999-02-04 Siemens Ag Procede et dispositif pour regler le seuil de decision et l'instant d'echantillonnage d'un regenerateur de donnees
WO1999012315A1 (fr) * 1997-09-02 1999-03-11 Siemens Aktiengesellschaft Circuit et procede pour minimiser les erreurs sur les bits

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100289714B1 (ko) 1997-08-21 2001-05-15 윤종용 데이터검출기및그방법
KR100289821B1 (ko) * 1997-08-21 2001-05-15 윤종용 데이터검출기및그방법
US6463109B1 (en) * 1998-08-25 2002-10-08 Vitesse Semiconductor Corporation Multiple channel adaptive data recovery system
US7224759B2 (en) * 2002-07-11 2007-05-29 Honeywell International Inc. Methods and apparatus for delay free phase shifting in correcting PLL phase offset
US7831855B2 (en) * 2007-04-12 2010-11-09 Harris Corporation System and method for generating a reset signal for synchronization of a signal
EP2031791A1 (fr) * 2007-08-30 2009-03-04 Deutsche Thomson OHG Appareil et procédé de récupération de données dans un signal d'entrée synchronisé

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3872432A (en) * 1974-04-10 1975-03-18 Itt Synchronization circuit for a viterbi decoder
US4675871A (en) * 1983-10-11 1987-06-23 Signal Processors Limited Digital data decoders
EP0504905A2 (fr) * 1991-03-20 1992-09-23 Nec Corporation Régulation de la récupération de porteuse avec détection séquentielle de synchronisation par autocorrection d'erreurs, et avec détection de synchronisation de trame
DE4308000A1 (de) * 1993-03-13 1994-09-15 Bosch Gmbh Robert Verfahren zur entscheidungsrückgekoppelten Taktableitung

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2505059A1 (fr) * 1981-04-30 1982-11-05 Jaeger Electrolyte a support organique, pour cellule d'affichage electrolytique
JPS6121660A (ja) * 1984-07-10 1986-01-30 Toshiba Corp 搬送波再生回路
SE462942B (sv) * 1989-01-26 1990-09-17 Ericsson Telefon Ab L M Saett och anordning foer snabb frekvensstyrning av en koherent radiomottagare
JPH03166839A (ja) * 1989-11-27 1991-07-18 Matsushita Electric Ind Co Ltd ディジタル情報検出装置
US5432820A (en) * 1990-11-19 1995-07-11 Fujitsu Limited Maximum-likelihood decoding method and device
DE4102800A1 (de) * 1991-01-31 1992-08-06 Thomson Brandt Gmbh Phasenregelkreis mit nachlaufsynchronisation
JP3259302B2 (ja) * 1992-01-28 2002-02-25 株式会社日立製作所 出力信号復号方法および装置
EP0644661B1 (fr) * 1993-09-20 2000-06-14 Canon Kabushiki Kaisha Appareil pour traiter des signaux
JPH07111042A (ja) * 1993-10-08 1995-04-25 Hitachi Ltd データ弁別回路
US5550870A (en) * 1994-03-02 1996-08-27 Lucent Technologies Inc. Viterbi processor
JP3015832B2 (ja) * 1995-06-27 2000-03-06 富士通株式会社 データ再生装置
JPH09214294A (ja) * 1996-02-08 1997-08-15 Fujitsu Ltd 自動周波数制御回路

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3872432A (en) * 1974-04-10 1975-03-18 Itt Synchronization circuit for a viterbi decoder
US4675871A (en) * 1983-10-11 1987-06-23 Signal Processors Limited Digital data decoders
EP0504905A2 (fr) * 1991-03-20 1992-09-23 Nec Corporation Régulation de la récupération de porteuse avec détection séquentielle de synchronisation par autocorrection d'erreurs, et avec détection de synchronisation de trame
DE4308000A1 (de) * 1993-03-13 1994-09-15 Bosch Gmbh Robert Verfahren zur entscheidungsrückgekoppelten Taktableitung

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
"CODE-ASSISTED BIT SYNCHRONISATION (CABS) SCHEME", ELECTRONICS LETTERS, vol. 25, no. 2, 19 January 1989 (1989-01-19), pages 152/153, XP000047686 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998049811A3 (fr) * 1997-04-25 1999-02-04 Siemens Ag Procede et dispositif pour regler le seuil de decision et l'instant d'echantillonnage d'un regenerateur de donnees
US6580763B1 (en) 1997-04-25 2003-06-17 Siemens Aktiengesellschaft Method and apparatus for controlling the decision threshold and sampling instant of a data generator
WO1999012315A1 (fr) * 1997-09-02 1999-03-11 Siemens Aktiengesellschaft Circuit et procede pour minimiser les erreurs sur les bits
US6625772B1 (en) 1997-09-02 2003-09-23 Siemens Aktiengesellschaft Circuit arrangement and method for minimizing bit errors

Also Published As

Publication number Publication date
MY113906A (en) 2002-06-29
ES2174994T3 (es) 2002-11-16
JPH08315518A (ja) 1996-11-29
DE19517405A1 (de) 1996-11-21
EP0744848B1 (fr) 2002-04-03
DE59608987D1 (de) 2002-05-08
US5940449A (en) 1999-08-17

Similar Documents

Publication Publication Date Title
DE3137906C2 (fr)
DE69620272T2 (de) Datenverabeitungsgerät und -verfahren
DE69524525T2 (de) Optimierung der Schreibprekompensation bei einem PRML-Kanal
DE69028516T2 (de) Lese-kanal-detektor zur anwendung in digitalen magnetaufzeichnungssystemen
DE69630784T2 (de) Datenverarbeitungsgerät und -verfahren
DE69623284T2 (de) Datenverarbeitungsgerät und -verfahren
DE19509876C2 (de) Verfahren und Schaltungsanordnung zur Aufbereitung eines von einem Aufzeichnungsträger wiedergegebenen Signals
DE68921173T2 (de) Datenaufzeichnungs-wiedergabegerät auf einer Aufzeichnungsscheibe.
DE3883907T2 (de) Vorrichtung zum Aufnehmen und Wiedergeben von digitalen Signalen.
DE69424908T2 (de) Signalverarbeitungsapparat
DE10018871A1 (de) Halbleitervorrichtung mit Entscheidungsrückkopplungsentzerrer
DE3420169A1 (de) Synchronsignal-detektorschaltung in einem digitalsignaluebertragungssystem
DE69617677T2 (de) Datenverarbeitungsgerät und -verfahren
DE69224936T2 (de) Auslesen von Signalen für optisches Speichermedium
DE69224872T2 (de) Entscheidungsgeführte Phasenverriegelte Schleife
DE69028827T2 (de) Verfahren und Vorrichtung zum Korrigieren der Phase eines Wiedergabetaktsignals
DE3126232A1 (de) Geraet zur wiedergabe eines informationssignal-aufzeichnungstraegers
EP0744848B1 (fr) Synchronisation d'un détecteur Viterbi avec rétroaction vers l'échantillonneur
DE69800600T2 (de) Digitalaufzeichungs-/-wiedergabegerät
DE69928641T2 (de) Erzeugung von amplitudenstufen für einen bitdetektor mit partieller wiedergabe und höchster wahrscheinlichkeit (prml)
DE2513922A1 (de) Pulscodemodulations-aufnahme- und -wiedergabegeraet
DE69420002T2 (de) Gerät zur Wiedergabe eines Videosignals
DE69018703T2 (de) Aufzeichnungs-Wiedergabegerät für Signale.
DE3108941A1 (de) Anordnung zur verhinderung von fehlerhaften korrekturen
DE69318929T2 (de) Vorrichtung zur Wiedergabe von digitalen Signalen

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): DE ES FR GB IT

17P Request for examination filed

Effective date: 19970521

17Q First examination report despatched

Effective date: 19990215

GRAG Despatch of communication of intention to grant

Free format text: ORIGINAL CODE: EPIDOS AGRA

GRAG Despatch of communication of intention to grant

Free format text: ORIGINAL CODE: EPIDOS AGRA

GRAG Despatch of communication of intention to grant

Free format text: ORIGINAL CODE: EPIDOS AGRA

GRAH Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOS IGRA

GRAH Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOS IGRA

REG Reference to a national code

Ref country code: GB

Ref legal event code: IF02

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE ES FR GB IT

RIC1 Information provided on ipc code assigned before grant

Free format text: 7H 04L 7/02 A, 7H 04L 25/03 B, 7H 03M 13/23 B

GBT Gb: translation of ep patent filed (gb section 77(6)(a)/1977)

Effective date: 20020403

REF Corresponds to:

Ref document number: 59608987

Country of ref document: DE

Date of ref document: 20020508

ET Fr: translation filed
REG Reference to a national code

Ref country code: ES

Ref legal event code: FG2A

Ref document number: 2174994

Country of ref document: ES

Kind code of ref document: T3

REG Reference to a national code

Ref country code: ES

Ref legal event code: GC2A

Effective date: 20021028

REG Reference to a national code

Ref country code: FR

Ref legal event code: D6

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed

Effective date: 20030106

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: ES

Payment date: 20120607

Year of fee payment: 17

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20130524

Year of fee payment: 18

Ref country code: DE

Payment date: 20130522

Year of fee payment: 18

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20130618

Year of fee payment: 18

Ref country code: IT

Payment date: 20130515

Year of fee payment: 18

REG Reference to a national code

Ref country code: DE

Ref legal event code: R119

Ref document number: 59608987

Country of ref document: DE

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20140507

REG Reference to a national code

Ref country code: DE

Ref legal event code: R119

Ref document number: 59608987

Country of ref document: DE

Effective date: 20141202

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST

Effective date: 20150130

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20141202

Ref country code: IT

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20140507

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20140602

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20140507

REG Reference to a national code

Ref country code: ES

Ref legal event code: FD2A

Effective date: 20150630

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: ES

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20140508