Classifications

• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
  • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
  • G09G5/39—Control of the bit-mapped memory
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
  • G06T1/00—General purpose image data processing
  • G06T1/60—Memory management
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2340/00—Aspects of display data processing
  • G09G2340/10—Mixing of images, i.e. displayed pixel being the result of an operation, e.g. adding, on the corresponding input pixels
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
  • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory

Definitions

• the present invention relates to an architecture with multiple input and output channels allowing the storage and transfer of fixed or animated video images.
• the invention relates to a new architecture allowing the implementation in real time of the operations mentioned above (transfer, storage) while respecting the "Broadcast” quality of the digital video images.
• “broadcast” quality is meant, for example, a representation of the data in 4: 2: 2: 4 format over 10 bits.
• the "frame buffer” is a physically localized memory, intended for the video function and specially adapted to the video format for which it was designed. If you want to work with several video channels, the information storage system must then be equipped with several specialized memories so that each video channel has a dedicated memory. If you want to have access to a large amount of information, it is then necessary to multiply the "frame buffers". A momentarily reduced use of the number of video channels then leads to a partial exploitation of the "frame buffers". This is a drawback.
• the present invention relates to an architecture for storing and transferring fixed or animated digital video images, said architecture comprising at least one input circuit allowing access to data intended to compose a video image, a memory area making it possible to store video images, at least one output circuit making it possible to extract at least one video channel from said architecture and a video bus intended to ensure the transfer of information between the memory area, the input circuit and the output circuit, characterized in that the memory area is an unmarked memory and in that the video bus has a width greater than or equal to the width of the memory area.
• the input circuit allowing the access of data intended to compose a video image can be directly a video input. It can also be an entry allowing you to draw video animations, or even a file type entry "bit map".
• the video frames constituting the different video channels are stored in a single unmarked memory.
• standard memory is meant a memory of which no part is particularly dedicated to a channel. Depending on the desired use, this memory can contain from a few units to several million frames or images.
• the architecture according to the invention makes it possible to use several channels simultaneously, each of which can consist of any sequence of frames available in the memory. It is then possible to modify, insert or delete frames in any sequence. The output of the system thus obtained can also be saved in the single memory and in turn become a source sequence.
• the system is advantageously independent of the size of the images, of the scanning system and of the frequencies of the video standard used at output.
• FIG. 1 shows the block diagram of the architecture according to the invention
• FIG. 2 shows a first application of the architecture according to the invention
• FIG. 3 shows a detail of the architectures of the figures - Figures 4 and 5 show 2 different embodiments of a second application of the architecture according to the invention.
• Figure 1 shows the block diagram of the architecture according to the invention.
• the memory M is a single generalized memory.
• the memory M can be of the DRAM type.
• the memory M is organized in words of width L, the size of which is adapted to the quantity of video frames which it is desired to process at a given instant.
• the width L is chosen as a function of the memory access time and the bit rate necessary to be able to process N video channels in real time in a given video scanning system.
• the width L can then be determined according to the following parameters:
• the width L then has the formula:
• the width L can be 320 bits which, for a DRAM memory working at 27 Mwords / sec and for a number b of bits per pixel equal to 32, results in a bit rate D equal to 27 x 320 / 8 MBytes / sec or 1080 Mbytes / sec. It is then possible to reach 20 simultaneous accesses at 54 MBytes / s.
• the memory M is controlled centrally by a control circuit CTRL.
• This control circuit allows memory management in real time.
• the principle of temporal memory management consists in that the data of each video channel is written or read in successive packets, each packet being the content of a block of memory, each channel being read in turn.
• This rotating access mechanism to each channel can, for example, work at the line frequency because whatever the cycle frequency, preferentially, each channel is allocated the same percentage of time, therefore the same flow.
• the physical space of each block is not defined in advance but is defined by a dynamic allocation of free memory at the time of recording. Access by blocks of consecutive words as described above advantageously allows sufficient time to be left between each block to allow the control circuit CTRL to find the next block of each of the channels and to initiate the physical transfer of the block.
• the dynamic management of the memory makes it possible to allocate only the memory necessary for each channel according to the needs. In particular, if a video channel is only partially active, the bit rate is reduced and only the necessary memory is consumed. It follows that the architecture according to the invention is particularly well suited to the management of images of variable sizes.
• the memory M is connected to a video bus B designed to provide the required video broadband.
• the video data exchange cycles are controlled by the memory M.
• the width of the video bus is equal to the width L of the memory M.
• FIG. 1 are represented not only input circuits (E1, E2,, En) and output circuits (S1, S2,, Sj), but also processing circuits (T1, T2,, Tm) of the video information.
• the video information processing circuits can be, for example, mixing circuits or else compression circuits.
• the invention relates both to architectures comprising processing circuits and to architectures not comprising processing circuits.
• T2,, Tm) and of output (S1, S2,, Sj) is connected to the video bus B by an interface circuit I having the function of transforming a port of great width located on the side of the video bus B into a port of video width located on the circuit side and operating continuously at normal video frequency.
• Such an interface circuit I comprises circuits commonly called FIFOs and has characteristics specific to the problem posed by the nature of the video signals to be processed and which will be specified later (cf. FIG. 3).
• a control bus BC makes it possible to control and command the various interface circuits I.
• FIG. 2 represents a first application of the architecture according to the invention.
• This application concerns a computer platform dedicated to image management in the Broadcast field.
• the devices concerned are then, for example, photo libraries, graphic palettes or even library libraries.
• An advantage of this first mode of application of the invention is to allow the simultaneous transfer of several video images between the different electronic cards of a broadcast video equipment using a standard computer platform, such as, for example, a standard PC platform.
• a standard computer platform such as, for example, a standard PC platform.
• PC Personal Computer
• the card K1 is an input card allowing access to a video signal on the input V and the card Kq is a card making it possible to output a video signal on two different outputs W1 and W2.
• the KM card and Ki cards can be, for example, electronic cards that each user can integrate into the PC for personal purposes. According to the preferred embodiment of the architecture shown in Figure 2, each PC user can process up to 8 videos in 4: 4: 4: 4 format simultaneously.
• the capacity of the KM memory card can be extended from 40 to 320 Mbytes. According to the preferred embodiment, the organization of the KM card allows it, in each cycle, access in read or write to a block of 4 pixels.
• the video bus of width L for example equal to 160 bits, makes it possible to transfer the blocks of 4 pixels at each cycle.
• the KM memory card and Ki cards are also connected to the standard BS bus of the PC.
• the video bus is independent of the bus BS of the host computer that constitutes the PC.
• bit rate is obtained, as mentioned previously, by spatial and temporal multiplexing of the data: a compromise between the size of the bus and its operating frequency makes it possible to size the characteristics of the multiplexing.
• the transfer of blocks of 4 pixels at a frequency of 25 MHz makes it possible to ensure an average bit rate greater than 8 videos in 4: 4: 4: 4, 10 bit format, in real time.
• the input card K1 can adapt to any type of format of the input signal.
• the same is true for the Kq output card.
• the control circuit CTRL is composed on the one hand of a specific electronic circuit located on the memory card KM and on the other hand of software executed by the central unit of the host PC.
• the specific electronic circuit located on the memory card KM generates all the control signals of the memory card KM, controls the interface circuits I of the cards Ki and operates at high frequencies compatible with the transfer rates of the data bus.
• the software executed by the central processing unit of the host PC sends to the specific electronic circuit mentioned above the parameters which represent the commands required by the operator operating the system.
• a computer platform such as that described above makes it possible to offer a user interface under DOS / Windows with the standard software utilities and tools as well as the communication tools, and in particular the Ethernet or FDDI network, capable of proposing an IT / client solution particularly suited to the need for managing still or moving images in a television studio.
• the Ki cards reserved for processing video information can be, for example, compression cards of the MJPEG, MPEG1 or MPEG2 type, making it possible to optimize the storage and the speed of transmission of the images via the network. For example, for a memory of 320 MBytes, the use of an MJPEG compression card makes it possible to achieve a recording time of 2 minutes of video.
• Ki cards can also be cards allowing to mix several video signals if the mixing function is desired.
• the architecture according to the invention can also be devoid of processing cards and include only input cards and output cards.
• FIG. 3 represents a detail of the architectures of FIGS. 1 and 2.
• FIG. 3 represents an example of an interface circuit I such as those mentioned in FIGS. 1 and 2.
• the video bus has a width of 160 bits .
• the interface circuit I makes it possible to process packets of 4 pixels, P1, P2, P3, P4.
• each pixel has four components C1 to C4 each of which is coded on 10 bits.
• Each interface circuit I comprises 4 circuits 11, 12, 13, 14 each collecting 40 bits on the bus side to restore 10 on the card side.
• the 40 bits collected by circuits 11, 12, 13 and 14 are respectively the 4 components C1, the 4 components C2, the 4 components C3 and the 4 components C4 of each of the 4 pixels P1, P2, P3, P4.
• circuit 1 1, 12, 13, 14 comprises a circuit 1 of the FIFO type and a rotary selector SR.
• circuit I also includes auxiliary circuits, such as bus drivers or FIFO control circuits, and which have not been shown in FIG. 3 so as not to unnecessarily burden the drawing.
• Clocks HB and HS respectively control the filling and removal of the bits contained in each FIFO type circuit 1.
• the interface circuit I comprises P circuits 1 of FIFO type and P rotary selectors SR so as to process packets of P pixels.
• each circuit 1 makes it possible to transform a port of large width located on the bus side into a port of conventional video width and operating continuously at regular frequency.
• the value of the video clock signal HC is then equal to P times that of the clock signal HS.
• the circuits 11, 12, 13, 14 according to the invention can be produced by discrete components or by ASICs while optimally ensuring their function .
• FIG. 4 represents a second application of the architecture according to the invention.
• the architecture according to the invention makes it possible to draw video animations directly on several independent levels and to develop the animated sequences in real time.
• all of the video frames constituting the different channels are stored one by one in the single memory M, which can contain from a few units to several million frames or images.
• Each of the video frames can be drawn or retouched, with simultaneous visual control, in the global memory without the use of a frame memory. It is possible to modify, insert or delete frames in any sequence.
• each image or video frame is stored in a well-defined local memory commonly known as a "frame buffer”.
• any graphics system uses the specific concept of image memory commonly called "bit map".
• the control circuit CTRL of the memory M consists of a specific processor 2 dedicated to the management of the memory in real time, which controls an access automaton 3.
• the processor 2 receives and executes video scrolling commands CV for each of the channels and manages the allocation and chaining of the blocks for each channel.
• the processor keeps the list of blocks with their address for each channel up to date and can thus initiate read or write transfers depending on the direction of the channel.
• the access controller 3 is a block transfer generator to the memory. It works entirely under the control of the memory management processor which provides it, for each block, with all the parameters of the transfer, namely: - start address;
• the controller 3 behaves as a consecutive memory access generator and, moreover, provides, via a control bus BC, the control signals making it possible to synchronize the FIFO type circuits contained in the interfaces I .
• one of the input circuits consists of an electronic drawing circuit 5 allowing, under the effect of the CD command and with visual control, the drawing or retouching of frames video stored in memory M.
• the architecture of the system which is the subject of the present application makes it possible to play simultaneously on several channels, each of which can consist of any sequence of frames available in the memory M.
• the mixing of the video sequences and the drawings is carried out in a multi-channel digital mixer 4.
• An interface circuit I such as that described above, is placed between each video channel coming from the high speed bus B and each input channel of the digital mixer 4.
• the desired video signal SV comes from of the mixer 4.
• the signal SV can be reintroduced into the bus B and in turn become a source sequence.
• the signal SV is not reintroduced into the bus B.
• FIG. 5 represents a second embodiment of the second application of the architecture according to the invention.
• This embodiment relates exclusively to a video system for animation of synthetic images. Write access in the memory M is then exclusively made with electronic drawing devices 5.

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• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• General Physics & Mathematics (AREA)
• Theoretical Computer Science (AREA)
• Computer Hardware Design (AREA)
• Controls And Circuits For Display Device (AREA)
• Studio Circuits (AREA)
• Bus Control (AREA)

Applications Claiming Priority (3)

Publications (1)

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ID=9479734

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• 1995
  • 1995-06-08 FR FR9506752A patent/FR2735318B1/fr not_active Expired - Fee Related
• 1996
  • 1996-06-07 EP EP96922076A patent/EP0775352A1/de not_active Withdrawn
  • 1996-06-07 JP JP9502693A patent/JPH10507294A/ja active Pending
  • 1996-06-07 US US08/776,384 patent/US6133961A/en not_active Expired - Fee Related
  • 1996-06-07 WO PCT/FR1996/000863 patent/WO1996042077A1/fr not_active Ceased

Patent Citations (1)

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