EP0810609A3 - Einzelelektron-Speicherzellenanordnung - Google Patents

Einzelelektron-Speicherzellenanordnung Download PDF

Info

Publication number
EP0810609A3
EP0810609A3 EP97107314A EP97107314A EP0810609A3 EP 0810609 A3 EP0810609 A3 EP 0810609A3 EP 97107314 A EP97107314 A EP 97107314A EP 97107314 A EP97107314 A EP 97107314A EP 0810609 A3 EP0810609 A3 EP 0810609A3
Authority
EP
European Patent Office
Prior art keywords
memory cell
cell device
single electron
electron memory
electron transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP97107314A
Other languages
English (en)
French (fr)
Other versions
EP0810609B1 (de
EP0810609A2 (de
Inventor
Lothar Dr. Risch
Wolfgang Dr. Rösner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Siemens AG
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG, Siemens Corp filed Critical Siemens AG
Publication of EP0810609A2 publication Critical patent/EP0810609A2/de
Publication of EP0810609A3 publication Critical patent/EP0810609A3/de
Application granted granted Critical
Publication of EP0810609B1 publication Critical patent/EP0810609B1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/02—Structural aspects of erasable programmable read-only memories
    • G11C2216/08—Nonvolatile memory wherein data storage is accomplished by storing relatively few electrons in the storage layer, i.e. single electron memory
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S977/00—Nanotechnology
    • Y10S977/902—Specified use of nanostructure
    • Y10S977/932—Specified use of nanostructure for electronic or optoelectronic application
    • Y10S977/936—Specified use of nanostructure for electronic or optoelectronic application in a transistor or 3-terminal device
    • Y10S977/937—Single electron transistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
  • Read Only Memory (AREA)

Abstract

Speicherzellen, die jeweils einen Einzelelektron-Transistor und ein Einzelelektron-Speicherelement umfassen und in denen der Einzelelektron-Transistor von einer im Speicherelement gespeicherten Ladung angesteuert wird, werden so dimensioniert, daß bei Anliegen einer Lesespannung ein von der gespeicherten Ladung abhängiger Strom durch den Einzelelektron-Transistor fließt, ohne die gespeicherte Ladung zu verändern. Bei Anliegen einer betragsmäßig größeren Schreibspannung wird die gespeicherte Ladung verändert. Die Speicherzellen werden jeweils zwischen erste Leitungen und quer dazu verlaufende zweite Leitungen einer Speicherzellenanordnung geschaltet.
EP97107314A 1996-05-31 1997-05-02 Einzelelektron-Speicherzellenanordnung Expired - Lifetime EP0810609B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19621994A DE19621994C1 (de) 1996-05-31 1996-05-31 Einzelelektron-Speicherzellenanordnung
DE19621994 1996-05-31

Publications (3)

Publication Number Publication Date
EP0810609A2 EP0810609A2 (de) 1997-12-03
EP0810609A3 true EP0810609A3 (de) 1999-08-11
EP0810609B1 EP0810609B1 (de) 2002-03-06

Family

ID=7795864

Family Applications (1)

Application Number Title Priority Date Filing Date
EP97107314A Expired - Lifetime EP0810609B1 (de) 1996-05-31 1997-05-02 Einzelelektron-Speicherzellenanordnung

Country Status (7)

Country Link
US (1) US5844834A (de)
EP (1) EP0810609B1 (de)
JP (1) JP4057675B2 (de)
KR (1) KR100435924B1 (de)
AT (1) ATE214194T1 (de)
DE (2) DE19621994C1 (de)
TW (1) TW382707B (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69825939T2 (de) 1997-05-30 2005-09-15 Matsushita Electric Industrial Co., Ltd., Kadoma Anordnung mit Quanten-Schachteln
DE19820050C1 (de) * 1998-05-05 1999-03-25 Siemens Ag Schaltungsanordnung mit Einzelelektron-Bauelementen und Verfahren zu deren Betrieb
KR100325689B1 (ko) 1999-12-01 2002-02-25 오길록 전자-홀 결합을 이용한 단전자 메모리 소자
US6653653B2 (en) 2001-07-13 2003-11-25 Quantum Logic Devices, Inc. Single-electron transistors and fabrication methods in which a projecting feature defines spacing between electrodes
US6483125B1 (en) 2001-07-13 2002-11-19 North Carolina State University Single electron transistors in which the thickness of an insulating layer defines spacing between electrodes
US6673717B1 (en) 2002-06-26 2004-01-06 Quantum Logic Devices, Inc. Methods for fabricating nanopores for single-electron devices
US7135697B2 (en) * 2004-02-25 2006-11-14 Wisconsin Alumni Research Foundation Spin readout and initialization in semiconductor quantum dots
US7602069B2 (en) * 2004-03-31 2009-10-13 Universität Duisburg-Essen Micro electronic component with electrically accessible metallic clusters
KR100673408B1 (ko) * 2005-02-07 2007-01-24 최중범 싱글 일렉트론 트랜지스터를 채용하는 메모리 셀 및 그메모리 장치
ATE376260T1 (de) * 2005-07-26 2007-11-15 Univ Duisburg Essen Mikroelektronisches bauelement
US20090066853A1 (en) * 2007-09-10 2009-03-12 Sony Corporation Sony Electronics Inc. Remote control with recessed keypad
US20120235968A1 (en) * 2011-03-15 2012-09-20 Qualcomm Mems Technologies, Inc. Method and apparatus for line time reduction
WO2015065337A1 (en) 2013-10-29 2015-05-07 Hewlett-Packard Development Company, L.P. Resistive crosspoint memory array sensing
US11047877B2 (en) * 2017-09-28 2021-06-29 Quantum Silicon Inc. Initiating and monitoring the evolution of single electrons within atom-defined structures

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5357460A (en) * 1991-05-28 1994-10-18 Sharp Kabushiki Kaisha Semiconductor memory device having two transistors and at least one ferroelectric film capacitor
DE4212220C3 (de) * 1992-04-09 2000-05-04 Guenter Schmid Verwendung einer Anordnung aus Clustermolekülen als mikroelektronisches Bauelement

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
KANUO YANO ET AL: "ROOM-TEMPERATURE SINGLE-ELECTRON MEMORY", IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 41, no. 9, 1 September 1994 (1994-09-01), pages 1628 - 1638, XP000466806 *
KAZUO YANO ET AL: "A ROOM-TEMPERATURE SINGLE-ELECTRON MEMORY DEVICE USING FINE-GRAIN POLYCRYSTALLINE SILICON", PROCEEDINGS OF THE INTERNATIONAL ELECTRON DEVICES MEETING, WASHINGTON, DEC. 5 - 8, 1993, 5 December 1993 (1993-12-05), INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, pages 541 - 544, XP000481675 *
NAKAZATO K ET AL: "SINGLE-ELECTRON MEMORY", ELECTRONICS LETTERS, vol. 29, no. 4, 18 February 1993 (1993-02-18), pages 384/385, XP000346076 *
NAKAZATO K ET AL: "SINGLE-ELECTRON MEMORY", JOURNAL OF APPLIED PHYSICS, vol. 75, no. 10, PART 01, 15 May 1994 (1994-05-15), pages 5123 - 5134, XP000456680 *

Also Published As

Publication number Publication date
JP4057675B2 (ja) 2008-03-05
KR100435924B1 (ko) 2004-07-16
DE59706533D1 (de) 2002-04-11
TW382707B (en) 2000-02-21
EP0810609B1 (de) 2002-03-06
ATE214194T1 (de) 2002-03-15
JPH1098160A (ja) 1998-04-14
US5844834A (en) 1998-12-01
EP0810609A2 (de) 1997-12-03
DE19621994C1 (de) 1997-06-12
KR970076815A (ko) 1997-12-12

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