EP1032027A2 - Procédé de formation d'un substrat assemblé comprenant une zone planaire de piégeage intrinsèque et substrat ainsi fabriqué - Google Patents

Procédé de formation d'un substrat assemblé comprenant une zone planaire de piégeage intrinsèque et substrat ainsi fabriqué Download PDF

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Publication number
EP1032027A2
EP1032027A2 EP00101783A EP00101783A EP1032027A2 EP 1032027 A2 EP1032027 A2 EP 1032027A2 EP 00101783 A EP00101783 A EP 00101783A EP 00101783 A EP00101783 A EP 00101783A EP 1032027 A2 EP1032027 A2 EP 1032027A2
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EP
European Patent Office
Prior art keywords
semiconductor material
layer
wafer
monocrystalline semiconductor
zone
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Application number
EP00101783A
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German (de)
English (en)
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EP1032027A3 (fr
Inventor
Jack Linn
William Speece
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Intersil Corp
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Intersil Corp
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Publication date
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Publication of EP1032027A2 publication Critical patent/EP1032027A2/fr
Publication of EP1032027A3 publication Critical patent/EP1032027A3/fr
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P36/00—Gettering within semiconductor bodies
    • H10P36/03—Gettering within semiconductor bodies within silicon bodies
    • H10P36/07—Gettering within semiconductor bodies within silicon bodies of silicon-on-insulator structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/061—Manufacture or treatment using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/977—Thinning or removal of substrate

Definitions

  • the present invention relates to gettering in a semiconductor device and, more particularly, to a process for forming a bonded semiconductor-on-insulator substrate containing a planar intrinsic gettering zone and to a semiconductor device and an integrated circuit formed on the bonded substrate.
  • a silicon wafer may be exposed to metallic contaminants such as iron, nickel, zinc, chromium, and the like that may ultimately degrade the final product yield, performance, or reliability. This contamination may occur through contact with stainless steel wafer handlers and tools, diffusion of metallic substances from heater coils or lamps in high temperature processing chambers, or sputter debris dislodging from plasma chamber walls.
  • Gettering is a term that refers generally to any mechanism by which contaminating impurities, typically transition metals, are removed from sensitive semiconductor device regions and entrapped in other relatively benign domains of the wafer. Gettering is described in Wolf and Tauber, Silicon Processing in the VLSI Era , Vol.1, 1986, Lattice Press, pp 61-70.
  • Gettering typically proceeds in three steps: 1) release of a contaminating element from its originating stable state and locale in the wafer into solid solution in the semiconductor crystal lattice; 2) diffusion of the contaminant through the crystal away from sensitive device structures or areas where susceptible structures are ultimately to be formed; and 3) capture of the contaminants by extended defects such as dislocations or precipitates at a position far enough away from devices to avoid interference with their operation and stable enough to prevent future liberation or discharge into the wafer during ensuing thermal, chemical and plasma treatments.
  • Extrinsic gettering entails the use of external means (usually on the wafer back surface) to create damage or stress in the silicon lattice, leading to the creation of extended defects capable of mobile metal capture.
  • Examples of extrinsic gettering approaches include: diffused backside phosphorus or arsenic doping to tie up nickel, gold, iron, copper, etc., and mechanical or physical backside wafer damage produced by abrasion, grooving, sandblasting, laser deformation, ion implantation, polysilicon deposition, etc.
  • Intrinsic gettering is typically accomplished by the localized capture of impurities at extended defects that exist within the bulk material of the silicon wafer, for example, a Czochralski grown monocrystalline wafer containing interstitial oxygen (5-25 ppma).
  • Intrinsic gettering usually involves the supersaturation of a region or zone of the silicon wafer with oxygen that will separate from solid solution and form clusters of silicon dioxide during thermal treatment.
  • the stresses resulting from the agglomerate clusters cause stacking faults and dislocation loops that are capable of trapping impurities.
  • the clusters must be formed in the bulk of the wafer away from active device sites. Oxygen levels above the precipitation threshold must therefore be avoided in regions where active devices will be later be formed and permanently reside.
  • U.S. Patent No. 5,229,305 describes a method for implanting boron, argon, krypton or, preferably, oxygen ions into a polished surface of a semiconductor layer, followed by thermal treatment, to create gettering sites in the layer.
  • the polished surface of the semiconductor layer is then bonded to a handle substrate, but does not show implanting silicon ions into the silicon substrate.
  • To create a high density gettering zone it requires a large implant dose. Such a dose of non-semiconductor ions would alter the electrical characteristics of the semiconductor substrate.
  • gettering techniques are inadequate for use with many desired semiconductor devices.
  • the formation of gettering sites by treatment of the back surface of a device is generally unsuited for application to semiconductor-on-insulator structures.
  • defects that provide gettering sites are often generated in an indiscriminate, scattered fashion throughout the wafer and may thus adversely affect the performance of a device subsequently formed in the wafer.
  • a method for making a bonded semiconductor-on-insulator substrate for integrated circuits that includes a high quality semiconductor device wafer having a smooth surface to promote its bonding integrity to a handle wafer and containing a well-defined, restricted intrinsic gettering zone close to but not detrimentally overlapping sites of devices that are particularly susceptible to metal contamination.
  • a semiconductor substrate whose electrical characteristics are substantially unchanged by the formation of a gettering zone therein. The present invention meets these needs.
  • the present invention is directed to a method for forming a bonded semiconductor-on-insulator substrate for the fabrication of semiconductor devices and integrated circuits.
  • ions of the semiconductor material are implanted to a selected depth in the wafer to form, adjacent to the surface, an amorphous layer of the semiconductor material.
  • the layer of amorphous semiconductor material extends to a substantially planar zone disposed at substantially the selected depth and comprising the monocrystalline semiconductor material damaged by lattice defects, i.e., end-of-range implant damage.
  • Undamaged material below the selected depth comprises a first layer of the monocrystalline semiconductor material.
  • the wafer is heated under conditions effective to convert the amorphous layer to a second layer of the monocrystalline semiconductor material and to coalesce the zone of damaged monocrystalline semiconductor material, thereby forming a substantially planar intrinsic gettering zone of substantially pure semiconductor material that includes active gettering sites disposed at substantially the selected depth.
  • the present invention includes a method for forming a bonded semiconductor-on-insulator substrate for semiconductor devices and integrated circuits, said steps of the method comprising a wafer having a monocrystalline semiconductor material, implanting ions of the semiconductor material through a surface of the monocrystalline semiconductor wafer to a selected depth in said wafer, so as to forming adjacent to said surface an amorphous layer of the semiconductor material, said amorphous semiconductor layer extending to a substantially planar zone disposed at substantially said selected depth and comprising monocrystalline semiconductor material damaged by lattice defects, undamaged monocrystalline semiconductor material below said selected depth comprising a first layer of the monocrystalline semiconductor material, heating said wafer under conditions effective to convert said amorphous semiconductor layer to a second layer of the monocrystalline semiconductor material, heating the wafer under conditions effective to coalesce said zone of monocrystalline semiconductor material damaged by lattice defects, thereby forming a substantially planar intrinsic gettering zone comprising substantially pure semiconductor material and including active gettering sites, said gettering zone being disposed substantially at said selected depth
  • An insulating bond layer on one surface of a handle wafer is bonded to the surface of the wafer to form a bonded semiconductor-on-insulator substrate comprising a handle wafer, an insulating bond layer, and a device wafer of monocrystalline semiconductor material.
  • the device wafer includes a substantially planar intrinsic gettering zone comprising substantially pure semiconductor material and including active gettering sites.
  • a bonded semiconductor-on-insulator substrate that includes a wafer comprising two layers of a monocrystalline semiconductor material separated by a planar intrinsic gettering zone that comprises substantially pure semiconductor material and contains active gettering sites.
  • the invention also includes a bonded semiconductor-on-insulator substrate for semiconductor devices and integrated circuits, said substrate comprising a wafer comprising a monocrystalline semiconductor material and having a first surface and a second surface, said wafer comprising a first layer of the monocrystalline semiconductor material adjacent to said first surface and a second layer of the monocrystalline semiconductor material adjacent to said second surface, and interposed between said first and second layers of the monocrystalline semiconductor material, a substantially planar intrinsic gettering zone comprising substantially pure semiconductor material and including active gettering sites, an insulating bond layer disposed on said second surface of said wafer; and a handle wafer bonded to said insulating bond layer, and a layer of epitaxial monocrystalline semiconductor material deposited on said second layer of monocrystalline semiconductor material, in which said monocrystalline semiconductor material comprises silicon and said implanted ions comprise silicon ions, and said handle wafer comprises silicon and said insulating bond layer comprises silicon dioxide, with said first layer of monocrystalline semiconductor material has a thickness of about 0.1 ⁇ m to about 0.8 ⁇ m, and
  • the bonded substrate of the present invention includes a narrowly restricted gettering zone located in near proximity to device regions, which increases the efficiency of contaminant removal from those regions and facilitates small geometry manufacture. Because the gettering zone comprises substantially pure semiconductor material, its formation affects only the structural characteristics and not the electrical characteristics of the wafer.
  • the bonded substrate of the invention is reliably constructed and provides excellent structural stability to devices formed on it over a wide range of processing temperature and conditions.
  • a bonded substrate 10 of the present invention includes a handle wafer 11 having on one surface 12 an insulating bond layer 13 and a semiconductor device wafer 14 bonded to insulating layer 13.
  • Semiconductor device wafer 14 has a first layer 15 of monocrystalline semiconductor material adjacent to insulating layer 13 and a second layer 16 of monocrystalline semiconductor material overlying first layer 15.
  • Second monocrystalline semiconductor layer 16 is separated from first monocrystalline semiconductor layer 15 by an intervening substantially planar intrinsic gettering zone 17 comprising gettering sites in the monocrystalline semiconductor material.
  • a further optional epitaxial monocrystalline semiconductor layer 18 can be deposited on surface 19 of layer 16.
  • FIGS. 2A-F depict the method of the invention for forming the device wafer 14 shown in FIG. 1.
  • an oxide layer 21 having a thickness preferably of about 1 nm to about 50 nm is optionally formed on a wafer 22 of monocrystalline semiconductor material.
  • the oxide of layer 21 may be a native oxide, a chemically grown oxide, a thermally grown oxide, or a deposited oxide.
  • Ions 23 of the semiconductor material at a dose of about to 10 14 to 10 18 ions/cm 2 are implanted, through oxide layer 21 if present, to a selected depth 24 in wafer 22, as shown in FIG. 2B.
  • the depth 24 of ion implantation can be controlled by the energy employed; for example, about 185 keV causes implantation of silicon ions at a depth 24 of about 0.4 ⁇ m, while a lower energy of about 90 keV results in a depth 24 of about 0.2 ⁇ m.
  • the depth of ion implantation in the monocrystalline semiconductor wafer preferably is about 0.1 ⁇ m to 2.0 ⁇ m, preferably about 0.2 ⁇ m to 0.6 ⁇ m, and the implantation energy preferably is about 50 keV to 250 keV. Ion implantation is well described in Giles, "Ion Implantation," Chapter 8 in Sze, editor, VLSI Technology , Second Edition, McGraw-Hill, Inc., 1988, the disclosure of which is incorporated herein by reference.
  • ion implantation results in formation of an amorphous semiconductor layer 25.
  • amorphous layer 25 may contain oxygen atoms that originated from layer 21.
  • a layer 26 of undamaged monocrystalline semiconductor material is separated from amorphous layer 25 by a substantially planar latent getter zone 27 of monocrystalline semiconductor material containing lattice defects, i.e., end-of-range implant damage.
  • Amorphous layer 25 is heated under conditions effective to convert it by solid phase epitaxial annealing to a layer 28 of monocrystalline semiconductor material, as shown in FIG. 2D.
  • the annealing of amorphous layer 25 to produce monocrystalline semiconductor layer 28 is achieved by heating to a temperature of about 450°C to 1200°C for about 15 minutes to 8 hours, preferably about 550°C to 620°C for about 2 hours to 6 hours in a non-oxidizing atmosphere such as nitrogen, argon, or hydrogen. Annealing removes from layer 28 sufficient oxygen to preclude the formation of defect sites.
  • gettering zone 17 comprises substantially pure semiconductor material containing dislocations that provide active gettering sites. Because implantation is carried out with ions 23 of the semiconductor material, e.g., silicon ions, no dopants or other contaminants that can affect the electrical properties of the semiconductor wafer 14 are introduced during ion implantation.
  • ions 23 of the semiconductor material e.g., silicon ions
  • Zone 27 can have an initial thickness of about 0.2 ⁇ m to 0.4 ⁇ m, coalescing to form a gettering zone 17 having a thickness of about 0.05 ⁇ m to about 0.2 ⁇ m, preferably about 0.1 ⁇ m.
  • First monocrystalline semiconductor layer 15 has a thickness of about 0.1 ⁇ m to about 0.8 ⁇ m, preferably about 0.2 ⁇ m to about 0.4 ⁇ m.
  • Second monocrystalline semiconductor layer 16, which is much thicker than layer 15, can have a thickness of 100 ⁇ m or greater prior to being thinned to a desired final thickness of about 0.2 ⁇ m to 20 ⁇ m.
  • FIG. 2F Removal of oxide layer 21, if present, produces device wafer 14, as shown in FIG. 2F. It should be noted that the structure of wafer 14 as shown in Fig. 2F is inverted relative to its orientation in FIG. 1.
  • FIG. 3 is a schematic representation of the formation of the bonded semiconductor-on-insulator substrate of the present invention by inverting device wafer 14, as shown in FIG. 2F, and bonding it to insulating bond layer 13 on handle wafer 11. Following bonding of wafer 14 to layer 12, thick second monocrystalline semiconductor layer 16 can be thinned to a desired thickness. An epitaxial monocrystalline semiconductor layer 18 can be deposited on thinned layer 16, as shown in FIG. 1, and active devices can be fabricated within epitaxial layer 18.
  • the planar gettering zone 17 can be precisely positioned at a depth 24 within device wafer 14.
  • the thickness of second monocrystalline semiconductor layer 16 can be controlled by chemical or mechanical material removal means, including etching, lapping, grinding, and polishing.
  • gettering zone 17 can also be precisely positioned with respect to devices formed on the surface 19 of layer 16 or in epitaxial layer 18.
  • the method of the present invention is applicable to any substrate having a semiconductor-on-insulator structure.
  • the semiconductor material comprising device wafer 14 is monocrystalline silicon, in which gettering zone 17 is produced by implanting silicon ions 23 through a layer 22 of silicon dioxide.
  • Semiconductor material comprising device wafer 14 can further be germanium, and gettering zone 17 can be produced by implanting germanium ions 23 through a layer 22 of germanium oxide.
  • Handle wafer 11 can be formed from a metal, an insulator, silicon carbide, polysilicon or, preferably, monocrystalline silicon.
  • Insulating bond layer can be formed of any insulating material but preferably comprises silicon dioxide.
  • the method of the present invention is especially useful for forming silicon-on-insulator (SOI) bonded substrates on which semiconductor devices and integrated circuits can be fabricated.
  • SOI silicon-on-insulator
  • FIG. 4 schematically depicts the cross-section of a bipolar junction transistor (BJT) 40 formed in an epitaxial layer 18 formed on a bonded SOI substrate 10 containing a planar intrinsic gettering zone 17 in accordance with the present invention.
  • Transistor 40 includes an emitter diffusion 42, a base diffusion 44, and a collector sinker diffusion 46.
  • the polarity of emitter diffusion 42 and sinker diffusion 46 are the same, i.e., n or p, the polarity of base diffusion 44 being the opposite, i.e., p or n.
  • Sinker diffusion 46 is connected to a buried layer 43. Insulating layers 48, 49, 50 isolate the respective metal contacts 52, 54, 56 for emitter, base, and sinker diffusions 42, 44, 46.
  • Surface insulator 51 protects an interconnect metal line 58 and otherwise seals the surface of transistor 40.
  • Lateral isolation trenches 60,61 which have oxide sidewalls and are filled with polysilicon, extend from the surface of transistor 40 to buried oxide insulating layer 13 and serve to isolate transistor 40 from adjacent devices.
  • resistors In addition to BJTs, many other types of devices can be constructed on the bonded substrate of the present invention: resistors, capacitors, diodes, field effect transistors (FETs), including junction and MOSFETs, thyristors, and the like.
  • FETs field effect transistors
  • a method for forming a bonded semiconductor-on-insulator substrate for the fabrication of semiconductor devices and integrated circuits a surface of a wafer of a monocrystalline semiconductor material is implanted with ions of the semiconductor material a to a selected depth in the wafer to form, adjacent to the surface, an amorphous layer of the semiconductor material.
  • the layer of amorphous semiconductor material extends to a substantially planar zone disposed at substantially the selected depth and comprising the monocrystalline semiconductor material damaged by lattice defects, i.e., end-of-range implant damage. Undamaged material below the selected depth comprises a first layer of the monocrystalline semiconductor material.
  • the wafer is heated under conditions effective to convert the amorphous layer to a second layer of the monocrystalline semiconductor material and to coalesce the zone of damaged monocrystalline semiconductor material, thereby forming a substantially planar intrinsic gettering zone of substantially pure semiconductor material that includes active gettering sites disposed at substantially the selected depth.
  • An insulating bond layer on one surface of a handle wafer is bonded to the surface of the wafer to form a bonded semiconductor-on-insulator substrate comprising a handle wafer, an insulating bond layer, and a device wafer of monocrystalline semiconductor material.

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  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)
  • Bipolar Transistors (AREA)
EP00101783A 1999-02-22 2000-01-28 Procédé de formation d'un substrat assemblé comprenant une zone planaire de piégeage intrinsèque et substrat ainsi fabriqué Withdrawn EP1032027A3 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US255231 1999-02-22
US09/255,231 US6255195B1 (en) 1999-02-22 1999-02-22 Method for forming a bonded substrate containing a planar intrinsic gettering zone and substrate formed by said method

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EP1032027A2 true EP1032027A2 (fr) 2000-08-30
EP1032027A3 EP1032027A3 (fr) 2004-11-24

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US6255195B1 (en) 2001-07-03
US20010016399A1 (en) 2001-08-23
US7052973B2 (en) 2006-05-30
US6825532B2 (en) 2004-11-30
JP2000260777A (ja) 2000-09-22
US20040180512A1 (en) 2004-09-16

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