EP1177579A1 - Porte-puce pour module puce, et procede de production du module puce - Google Patents

Porte-puce pour module puce, et procede de production du module puce

Info

Publication number
EP1177579A1
EP1177579A1 EP00936667A EP00936667A EP1177579A1 EP 1177579 A1 EP1177579 A1 EP 1177579A1 EP 00936667 A EP00936667 A EP 00936667A EP 00936667 A EP00936667 A EP 00936667A EP 1177579 A1 EP1177579 A1 EP 1177579A1
Authority
EP
European Patent Office
Prior art keywords
chip
tapes
connection
carrier film
carrier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP00936667A
Other languages
German (de)
English (en)
Inventor
David Finn
Manfred Rietzler
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Smartrac IP BV
Original Assignee
Finn David
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Finn David filed Critical Finn David
Publication of EP1177579A1 publication Critical patent/EP1177579A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07745—Mounting details of integrated circuit chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/688—Flexible insulating substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

  • Chip carrier for a chip module and method for producing the chip module are provided.
  • the present invention relates to a chip carrier with a substrate and connection conductors arranged on the substrate, the connection conductors being in the form of strips and extending in parallel over the substrate. Furthermore, the invention relates to a chip module produced using the chip carrier and to a method for producing such a chip module.
  • Chip carriers are usually used to produce chip modules, which are provided on their surface with a conductor track structure for connection with increased contact metallizations of the chip.
  • the use of conductor track structures produced by etching processes does indeed allow any and in particular complex conductor track structures.
  • the provision or manufacture of the customary chip carriers, independently of the actual contacting process with the chip for producing the chip module already requires a complex and correspondingly complex procedure.
  • the use of etching techniques requires a corresponding structure of the carrier layer of the substrate, which in addition to a so-called etch stop layer must also be provided with a lacquer coating when using lithographic processes to define the conductor track structure.
  • a chip module with a chip carrier in which the connection conductors formed on an insulation layer extend in the form of strips and arranged parallel to one another over the insulation layer of the substrate and are each associated with an increased contact metallization of a chip.
  • the individual substrates of the chip carriers are arranged on an endless substrate carrier which is connected to the individual substrates via the connecting conductors which extend continuously over the substrate carrier.
  • the film-like substrate carrier is only used to connect the connecting conductors to the substrate.
  • the object of the invention is to provide a chip carrier for a chip module or a method for producing a chip module which has a particularly simple structure compared to the known chip modules and thus opens up the possibility of particularly cost-effective production.
  • the connecting conductors consist of electrically conductive connecting tapes applied to the substrate, and the substrate is formed by a carrier film.
  • connection conductors Due to the design of the connection conductors as connection tapes, which are independent of the carrier film in their formation, the connection conductors can be dispensed with using complex etching technology.
  • the chip carrier according to the invention therefore consists of a Combination of a carrier film and connecting tapes, each of which is an independent element in the initial state, so that no special technologies, such as the use of an etching process, but rather a simple connection or joining process is sufficient for producing the chip carrier, the
  • Substrate is formed directly by the carrier film.
  • the substrate By forming the substrate as a carrier film, particularly flat substrates are also possible.
  • the carrier film is provided on its side opposite the connecting tapes with at least one further conductive tape in such a way that the insulating carrier film is arranged as an intermediate layer between the connecting tapes on the one hand and the further conductive tape on the other.
  • a capacitor structure is realized, which is arranged in parallel connection with the chip after contacting the connection tapes with a chip.
  • This particular structure of the chip module opens up the particular advantage, particularly in the field of transponder technology, when contacting the connecting tapes with a coil unit that the range of the transponder unit formed by the combination of the chip and the coil unit can be significantly increased.
  • connection material order can, for example, come from a connection solder order or also consist of the application of an electrically conductive adhesive or the like.
  • connection tapes are provided, at least in sections, with a contact metallization for contacting with the increased contact metallizations of the chip, particularly high quality, i.e. Realize reliable connections, in particular due to the improved surface quality of the connection tapes due to the contact metallization.
  • connection tapes of the chip carrier are connected to connection ends of a coil unit
  • the chip carrier can serve as a base unit for the production of a transponder unit, such that the base unit only has to be supplemented by contacting a chip.
  • connection tapes contacted with the contact metallizations of the chip are also connected to connection ends of a coil unit.
  • the contact metallizations of the chip are contacted with the top of the connection strips of the chip carrier.
  • this structure of the chip module offers the advantage that the side of the substrate opposite the connecting strips is available for further applications. If, in addition, the connection tapes contacted with the contact metalizations of the chip are connected to connection ends of a coil unit, a transponder module with a particularly simple construction is created.
  • the method according to the invention for producing a chip module has the method steps:
  • connection tapes Application of at least two electrically conductive connection tapes on one side of a carrier film, such that the connection tapes extend in a parallel arrangement over the carrier film, and
  • connection tapes In such a way that a contact metallization of the chip is contacted with a connection tape.
  • the production process is characterized by the smallest possible number of process steps, due to the fact that the substrate provided with connecting conductors is realized by a simple combination of connecting tapes with a carrier film and the type of contacting according to the invention is simple Allows flip-chip contacting.
  • a first part of the production process which can also be carried out independently of the subsequent contacting with the chip, realizes as an intermediate product a chip carrier which is directly used for the production can be used by transponder units.
  • connection tapes are applied continuously to the carrier film in such a way that the connection tapes and the carrier film are provided as endless tapes and are continuously moved against one another in a contact area with the formation of liability.
  • the carrier film is provided with window openings at defined intervals prior to the formation of the contact area with the connection tapes, such that the window openings in the contact area subsequently formed are covered by the connection tapes with the formation of pocket-shaped contact receptacles, the production of a chip module is also effected without influencing a continuous process sequence possible, in which the contact metallizations of the chip are contacted with the underside of the connection tapes and the chip itself is on the side of the carrier film opposite the connection tapes.
  • This process variant thus enables the production of a particularly flat or thin chip module.
  • the carrier film is coated on the side opposite the side intended for the application of the connection tapes with at least one further electrically conductive counter tape. This process can take place before application of the connection tapes or after application of the connection tapes on the carrier film.
  • a particularly simple and therefore also inexpensive implementation of the method is possible if the connecting tapes and / or the at least one counter-tape are applied to the carrier film in a lamination process.
  • Fig. 1 shows a chip carrier for producing a chip module in
  • FIG. 2 shows the chip carrier shown in FIG. 1 with a chip contacted thereon to form a chip module
  • Fig. 3 shows a first embodiment of a chip module in a
  • Fig. 4 shows a second embodiment of the chip module in one
  • FIG. 5 shows a third embodiment of a chip module in a sectional view
  • Fig. 6 is an electrical equivalent diagram for the substrate of the in
  • Fig. 5 shown chip module
  • Fig. 7 is a schematic representation of a device for
  • FIG. 1 shows a plan view of a section of a chip carrier tape 10 with a carrier film 11 and connecting tapes 12 and 13 applied to one side of the carrier film 11.
  • FIG. 2 shows the chip carrier tape 10 shown in FIG. 1 with a plurality of chips 14 contacted at a distance from one another on the chip carrier tape 10.
  • the chips 14 are in each case with their contact metallizations, which in technical terms are also referred to as “ Bumps "are referred to, contacted with the connection tapes 12, 13 in flip-chip technology, such that one bump 15 or 16 is assigned to a connection tape 12, 13 in an electrically conductive manner.
  • chip modules 18 are passed through after contacting the chips 14 with the chip carrier tape 10 Separating cuts are released by the chip carrier tape 10 from the chip module assembly held together by the chip carrier tape 10.
  • Fig. 3 shows a sectional view according to section line III-III in Fig. 2.
  • the chip 14 is in flip-chip technology with its bumps 15, 16 on the connecting tapes 12, 13 along the
  • the carrier film 11 forming the substrate of the chip carrier 19 is made of Kapton, which is covered on its upper side with the connecting strips 12, 13 made of so-called E-copper. To improve the surface quality of the connecting strips 12, 13, in the present case they are coated with a contact metallization.
  • Other electrically non-conductive materials such as, for example, epoxy glass, polyester, polycarbonate and polyimide, can also be used for the chip carrier 19 or the chip carrier tape 10, in particular when using a manufacturing method, such as the following with reference to FIG. 7 explained in more detail, a flexible design of the carrier film 1 1, for example made of polyimide, is advantageous.
  • FIG. 4 shows a variant of a chip module 20 in which, in contrast to the chip module 18 shown in FIG. 3, in which the chip 14 is contacted with an upper side 21 of the connecting strips 12, 13, the chip 14 is contacted with a Bottom 22 of the connecting tapes 12, 13 is carried out.
  • pocket-shaped contact receptacles 23, 24 are formed in the areas of the carrier film 11 of a chip carrier covered by the connecting tapes 12, 13, which serve to receive the bumps 15, 16 of the chip 14.
  • a separate connecting material such as a solder material 25 is additionally arranged between the undersides 22 of the connecting strips 12, 13 and the bumps 15, 16 of the chip 14.
  • FIG. 5 shows in a further embodiment a chip module 26, in which, in contrast to the chip module 18 shown in FIG. 3, a counterband 27 is provided on the side of the carrier film 11 opposite the connecting tapes 12, 13, which in the same way as that Connection tapes 12, 13 is applied to the carrier film 1 1 and can consist of the same material as the connection tapes 12, 13.
  • FIG. 6 Due to the construction shown in FIG. 5, consisting of mutually opposite connecting strips 12, 13 on the one hand and the counter-strip 27 on the other hand, separated by an insulating intermediate layer in the form of the carrier film 11, a capacitor arrangement is realized electrically, the equivalent diagram of which is shown in FIG. 6 is. According to FIG. 6, the construction of the substrate 28 electrically results in a series connection of two capacitors which are arranged in parallel with the chip 14.
  • FIG. 7 shows a possible variant for producing a chip module, the system structure shown in FIG. 7 in particular making it possible to manufacture the chip module 20 shown in FIG. 4 in an endless and coherent arrangement.
  • the system shown schematically in FIG. 7 comprises a supply roll 30 with a carrier film 11 arranged thereon, which is unwound in the direction of arrow 31 and is wound on a product roll 32 at the end of the system.
  • the intermediate area of the supply roll 30 and the product roll 32 there are two supply rolls 33 and 34 with a wound-up connecting tape 12 and 13, respectively.
  • a laminating roller 35 Between the supply rolls 33 and 34 on the one hand and the product roll 32 on the other hand there is a laminating roller 35.
  • the laminating roller 35 is formed with the chip carrier 28 shown in section in FIG. 4 in an endless form and is wound up on the product roll 32.
  • the product roll 32 can in turn now be used as a supply roll for a subsequent production process for the continuous or clocked contacting of chips 14 with the connecting strips 12, 13, so that chip modules 20 can be produced in an endlessly contiguous arrangement, as shown in FIG. 4.
  • coil units can also be contacted with the connecting tapes following the lamination process.
  • the design of the coils is arbitrary.
  • the coils can be arranged on a separate carrier or, in a particularly advantageous manner, applied without a carrier and directly to the carrier film and contacted with the connecting tapes. In this context, the use of wire coils proves to be advantageous.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Wire Bonding (AREA)
  • Credit Cards Or The Like (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Manufacturing Cores, Coils, And Magnets (AREA)

Abstract

L'invention concerne un porte-puce utilisé pour la constitution d'un module puce (18), qui comporte un substrat et des conducteurs de raccordement disposés sur ce substrat. Les conducteurs de raccordement se présentent sous la forme de bandes et s'étendent parallèlement sur le substrat. Ces connecteurs de raccordement sont constitués de rubans de connexion (12, 13) électroconducteurs, appliqués sur le substrat, et le substrat est formé par un film support (11).
EP00936667A 1999-05-05 2000-05-04 Porte-puce pour module puce, et procede de production du module puce Withdrawn EP1177579A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19920593 1999-05-05
DE19920593A DE19920593B4 (de) 1999-05-05 1999-05-05 Chipträger für ein Chipmodul und Verfahren zur Herstellung des Chipmoduls
PCT/DE2000/001396 WO2000068994A1 (fr) 1999-05-05 2000-05-04 Porte-puce pour module puce, et procede de production du module puce

Publications (1)

Publication Number Publication Date
EP1177579A1 true EP1177579A1 (fr) 2002-02-06

Family

ID=7907006

Family Applications (1)

Application Number Title Priority Date Filing Date
EP00936667A Withdrawn EP1177579A1 (fr) 1999-05-05 2000-05-04 Porte-puce pour module puce, et procede de production du module puce

Country Status (9)

Country Link
US (1) US7105915B1 (fr)
EP (1) EP1177579A1 (fr)
JP (2) JP2002544671A (fr)
KR (1) KR100763572B1 (fr)
CN (1) CN1200460C (fr)
AU (1) AU5208000A (fr)
CA (1) CA2370878C (fr)
DE (1) DE19920593B4 (fr)
WO (1) WO2000068994A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7971339B2 (en) 2006-09-26 2011-07-05 Hid Global Gmbh Method and apparatus for making a radio frequency inlay
US8286332B2 (en) 2006-09-26 2012-10-16 Hid Global Gmbh Method and apparatus for making a radio frequency inlay
US8413316B2 (en) 2007-09-18 2013-04-09 Hid Global Ireland Teoranta Method for bonding a wire conductor laid on a substrate

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1215725A3 (fr) * 2000-12-18 2005-03-23 cubit electronics Gmbh Assemblage utilisé pour supporter des dispositifs électriques et transpondeur sans contacts
DE10151657C1 (de) * 2001-08-02 2003-02-06 Fraunhofer Ges Forschung Verfahren zur Montage eines Chips auf einem Substrat
US6859057B2 (en) * 2002-09-17 2005-02-22 Aehr Test Systems Die carrier
DE10358422B3 (de) * 2003-08-26 2005-04-28 Muehlbauer Ag Verfahren zur Herstellung von Modulbrücken
US20050129977A1 (en) * 2003-12-12 2005-06-16 General Electric Company Method and apparatus for forming patterned coated films
TWI288885B (en) * 2004-06-24 2007-10-21 Checkpoint Systems Inc Die attach area cut-on-fly method and apparatus
AU2005304141B2 (en) * 2004-11-02 2010-08-26 Hid Global Gmbh Laying device, contacting device, advancing system, laying and contacting unit, production system, method for the production and a transponder unit
DE102005044306A1 (de) * 2005-09-16 2007-03-22 Polyic Gmbh & Co. Kg Elektronische Schaltung und Verfahren zur Herstellung einer solchen
US7546671B2 (en) 2006-09-26 2009-06-16 Micromechanic And Automation Technology Ltd. Method of forming an inlay substrate having an antenna wire
US8608080B2 (en) 2006-09-26 2013-12-17 Feinics Amatech Teoranta Inlays for security documents
US8322624B2 (en) 2007-04-10 2012-12-04 Feinics Amatech Teoranta Smart card with switchable matching antenna
US7979975B2 (en) 2007-04-10 2011-07-19 Feinics Amatech Teavanta Methods of connecting an antenna to a transponder chip
US7581308B2 (en) 2007-01-01 2009-09-01 Advanced Microelectronic And Automation Technology Ltd. Methods of connecting an antenna to a transponder chip
DE102006047388A1 (de) 2006-10-06 2008-04-17 Polyic Gmbh & Co. Kg Feldeffekttransistor sowie elektrische Schaltung
US7980477B2 (en) 2007-05-17 2011-07-19 Féinics Amatech Teoranta Dual interface inlays
DE102008016274A1 (de) 2008-03-28 2009-10-01 Smartrac Ip B.V. Chipträger für ein Transpondermodul sowie Transpondermodul
DE102009012255A1 (de) 2009-03-07 2010-09-09 Michalk, Manfred, Dr. Schaltungsanordnung
DE102009056122A1 (de) * 2009-11-30 2011-06-01 Smartrac Ip B.V. Verfahren zur Kontaktierung eines Chips
DE102012200258A1 (de) * 2012-01-10 2013-07-11 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Verfahren zur herstellung eines chips
DE102012209328A1 (de) 2012-06-01 2013-12-05 3D-Micromac Ag Verfahren und Anlage zum Herstellen eines Mehrschichtelements sowie Mehrschichtelement

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3440027A (en) * 1966-06-22 1969-04-22 Frances Hugle Automated packaging of semiconductors

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3691628A (en) * 1969-10-31 1972-09-19 Gen Electric Method of fabricating composite integrated circuits
US3855693A (en) * 1973-04-18 1974-12-24 Honeywell Inf Systems Method for assembling microelectronic apparatus
US4125810A (en) * 1977-04-08 1978-11-14 Vari-L Company, Inc. Broadband high frequency baluns and mixer
US4151579A (en) * 1977-09-09 1979-04-24 Avx Corporation Chip capacitor device
JPH01217934A (ja) * 1988-02-26 1989-08-31 Hitachi Ltd キャリアテープ
US5122929A (en) * 1988-08-16 1992-06-16 Delco Electronics Corporation Method of achieving selective inhibition and control of adhesion in thick-film conductors
US5176853A (en) * 1988-08-16 1993-01-05 Delco Electronics Corporation Controlled adhesion conductor
FR2645680B1 (fr) 1989-04-07 1994-04-29 Thomson Microelectronics Sa Sg Encapsulation de modules electroniques et procede de fabrication
JPH03120746A (ja) * 1989-10-03 1991-05-22 Matsushita Electric Ind Co Ltd 半導体素子パッケージおよび半導体素子パッケージ搭載配線回路基板
FR2673041A1 (fr) * 1991-02-19 1992-08-21 Gemplus Card Int Procede de fabrication de micromodules de circuit integre et micromodule correspondant.
US5635751A (en) * 1991-09-05 1997-06-03 Mitsubishi Denki Kabushiki Kaisha High frequency transistor with reduced parasitic inductance
JP3241139B2 (ja) * 1993-02-04 2001-12-25 三菱電機株式会社 フィルムキャリア信号伝送線路
US5385785A (en) * 1993-08-27 1995-01-31 Tapeswitch Corporation Of America Apparatus and method for providing high temperature conductive-resistant coating, medium and articles
DE4416697A1 (de) 1994-05-11 1995-11-16 Giesecke & Devrient Gmbh Datenträger mit integriertem Schaltkreis
US5528222A (en) 1994-09-09 1996-06-18 International Business Machines Corporation Radio frequency circuit and memory in thin flexible package
WO1996013728A1 (fr) * 1994-10-28 1996-05-09 Nitto Denko Corporation Structure de sonde
JP3484554B2 (ja) 1995-02-28 2004-01-06 日本テキサス・インスツルメンツ株式会社 半導体装置
DE19509999C2 (de) * 1995-03-22 1998-04-16 David Finn Verfahren und Vorrichtung zur Herstellung einer Transpondereinheit sowie Transpondereinheit
EP0742682B1 (fr) * 1995-05-12 2005-02-23 STMicroelectronics, Inc. Système de conditionnement pour circuit intégré par socle à profil bas
US5681662A (en) * 1995-09-15 1997-10-28 Olin Corporation Copper alloy foils for flexible circuits
DE19541039B4 (de) * 1995-11-03 2006-03-16 Assa Abloy Identification Technology Group Ab Chip-Modul sowie Verfahren zu dessen Herstellung
DE19601203A1 (de) 1996-01-15 1997-03-20 Siemens Ag Datenträgerkarte und Verfahren zu deren Herstellung
US5847929A (en) * 1996-06-28 1998-12-08 International Business Machines Corporation Attaching heat sinks directly to flip chips and ceramic chip carriers
DE19639646A1 (de) 1996-09-26 1998-04-02 Siemens Ag Trägerband und Verfahren zum Herstellen eines solchen Trägerbandes
TW480636B (en) * 1996-12-04 2002-03-21 Seiko Epson Corp Electronic component and semiconductor device, method for manufacturing and mounting thereof, and circuit board and electronic equipment
DE19651566B4 (de) * 1996-12-11 2006-09-07 Assa Abloy Identification Technology Group Ab Chip-Modul sowie Verfahren zu dessen Herstellung und eine Chip-Karte
FR2756955B1 (fr) 1996-12-11 1999-01-08 Schlumberger Ind Sa Procede de realisation d'un circuit electronique pour une carte a memoire sans contact
JPH113411A (ja) * 1997-06-13 1999-01-06 Hitachi Chem Co Ltd Ｉｃカード
US6040702A (en) * 1997-07-03 2000-03-21 Micron Technology, Inc. Carrier and system for testing bumped semiconductor components
US6057174A (en) * 1998-01-07 2000-05-02 Seiko Epson Corporation Semiconductor device, method of fabricating the same, and electronic apparatus
KR100395188B1 (ko) * 1998-01-12 2003-08-21 세이코 엡슨 가부시키가이샤 반도체장치 및 그 제조방법과 전자기기
US6815251B1 (en) * 1999-02-01 2004-11-09 Micron Technology, Inc. High density modularity for IC's

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3440027A (en) * 1966-06-22 1969-04-22 Frances Hugle Automated packaging of semiconductors

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7971339B2 (en) 2006-09-26 2011-07-05 Hid Global Gmbh Method and apparatus for making a radio frequency inlay
US8286332B2 (en) 2006-09-26 2012-10-16 Hid Global Gmbh Method and apparatus for making a radio frequency inlay
US8413316B2 (en) 2007-09-18 2013-04-09 Hid Global Ireland Teoranta Method for bonding a wire conductor laid on a substrate

Also Published As

Publication number Publication date
WO2000068994A1 (fr) 2000-11-16
AU5208000A (en) 2000-11-21
CA2370878C (fr) 2011-02-15
KR100763572B1 (ko) 2007-10-04
JP2011101037A (ja) 2011-05-19
CN1200460C (zh) 2005-05-04
DE19920593A1 (de) 2000-11-23
JP5444261B2 (ja) 2014-03-19
CN1360736A (zh) 2002-07-24
JP2002544671A (ja) 2002-12-24
US7105915B1 (en) 2006-09-12
CA2370878A1 (fr) 2000-11-16
DE19920593B4 (de) 2006-07-13
KR20020008400A (ko) 2002-01-30

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