EP1238426A2 - Ensemble boitier d'un composant a semi-conducteur - Google Patents

Ensemble boitier d'un composant a semi-conducteur

Info

Publication number
EP1238426A2
EP1238426A2 EP00990529A EP00990529A EP1238426A2 EP 1238426 A2 EP1238426 A2 EP 1238426A2 EP 00990529 A EP00990529 A EP 00990529A EP 00990529 A EP00990529 A EP 00990529A EP 1238426 A2 EP1238426 A2 EP 1238426A2
Authority
EP
European Patent Office
Prior art keywords
semiconductor chip
arrangement according
circuit board
shaped element
metal layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP00990529A
Other languages
German (de)
English (en)
Inventor
Simon Muff
Friedrich Wanninger
Jens Pohl
Christian Hauser
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1238426A2 publication Critical patent/EP1238426A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/22—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections
    • H10W40/226—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections characterised by projecting parts, e.g. fins to increase surface area
    • H10W40/228—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections characterised by projecting parts, e.g. fins to increase surface area the projecting parts being wire-shaped or pin-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/013—Manufacture or treatment of die-attach connectors
    • H10W72/01308—Manufacture or treatment of die-attach connectors using permanent auxiliary members, e.g. using alignment marks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07311—Treating the bonding area before connecting, e.g. by applying flux or cleaning

Definitions

  • the present invention relates to a housing arrangement of a semiconductor module, which comprises a printed circuit board, a semiconductor chip and an intermediate carrier layer for rewiring the wiring connections of the semiconductor chip to the printed circuit board, in which the carrier layer is contacted with the printed circuit board via soldering points and the soldering points from the semiconductor chip via a filler are mechanically decoupled.
  • Integrated semiconductor circuits are used in different applications.
  • a semiconductor chip is generally packaged in a housing and placed on a circuit board.
  • a semiconductor component is arranged in a housing arrangement in accordance with a so-called FBGA housing arrangement (FBGA: Fine Pitch Ball Grid Array), which is based in particular on the so-called beam lead bonding technology.
  • FBGA Fine Pitch Ball Grid Array
  • This type of housing arrangement is characterized in particular by a special housing design with regard to the arrangement of the solder balls.
  • a housing arrangement such as the FBGA housing arrangement, also referred to as an FBGA package, usually comprises a semiconductor chip with connections for electrical connection to connections on the printed circuit board, and a carrier layer, which functions as a type of rewiring level.
  • the carrier layer is arranged between the semiconductor chip and the printed circuit board.
  • the carrier layer as the rewiring level has electrically conductive connections to the connections of the semiconductor chip, these conductor tracks of the carrier layer in turn are connected to the circuit board via solder joints. Since the
  • a filler also called an encapsulant or cushion material, is provided between the semiconductor chip and the carrier layer.
  • heat sinks are heat sinks that are usually cooled externally and therefore assume a constant temperature. With the help of heat spreaders, for example, a larger area is created that better dissipates the heat to the outside via convection.
  • the execution takes place, for example, by means of metal plates which are fastened to the housing or are introduced directly into the housing.
  • the main heat path in the described type of housing arrangements for dissipating the power loss is the distance from the semiconductor chip via the filler material and the solder balls to the printed circuit board.
  • the relatively poor thermal conductivity of the filling material or cushioning material limits the thermal resistance of the housing. If the housing has limited thermal conductivity, the dissipatable power loss is limited, which can also limit the performance of an integrated semiconductor circuit.
  • the use of thermally conductive full material or cushion material makes it possible to improve the thermal conductivity of the main heat path. However, this method
  • the object of the present invention is to provide an arrangement of a semiconductor device in the described housing arrangement, which has an improved conductivity of the dissipated power to be dissipated in a built-in semiconductor chip and in which the mechanical properties of the housing arrangement are retained.
  • the arrangement has a semiconductor chip with wiring connections and a printed circuit board on which the semiconductor module is placed, and a carrier layer which is arranged between the semiconductor chip and the printed circuit board.
  • the carrier layer serves for rewiring the wiring connections of the semiconductor chip to the printed circuit board and is connected to the printed circuit board via solder joints.
  • a filler which serves for the mechanical decoupling of the semiconductor chip and the solder points, is arranged between the semiconductor chip and the carrier layer.
  • a metal layer is applied to the carrier layer, which is coated with at least one of the solder places is connected.
  • at least one shaped element made of heat-dissipating material is applied to the metal layer and connected to it in a heat-conducting manner.
  • the conductivity of the heat dissipation of the housing arrangement to be dissipated is improved by the provision of the heat-conducting molded element.
  • the previously used full material with the desired properties can be provided as the filler.
  • the shaped element serves, for example, to reduce the distance between the carrier layer, also referred to as an interposer, and the semiconductor chip in places, and thus to bridge the relatively poor thermal conductivity of the full material.
  • a further possible warm path which contributes to the dissipation of the power loss generated, can be created by a corresponding local arrangement of the molded element.
  • the transported heat is transferred to the metal layer of the carrier layer and from there via the solder points into the metal surfaces of the printed circuit board. Accordingly, the heat-dissipating molded element has the function of a heat sink compared to the semiconductor chip. So that the mechanical properties of the housing arrangement are not influenced by the molded element, the molded element is not in direct contact with the semiconductor chip.
  • the structure of the housing arrangement described is used in particular in FBGA housing arrangements.
  • the shaped element is suitably arranged in such a way that it protrudes into the filler.
  • the shaped element is preferably designed as a cylinder.
  • a metal layer in the form of large interconnected metal surfaces is applied to the carrier layer.
  • the thermal conductivity and its distribution is favored by applying several relatively small cylinders to the metal layer. Since metal has a good Wär ⁇ meleitschreib, the mold members are preferably formed of metal.
  • the described structure of the metal layer and shaped elements can e.g. be produced by a mask etching process or by electroplating the shaped elements.
  • the shaped elements or cylinders are embedded in the filling material before the semiconductor chip is assembled. In the assembled state, the shaped elements or cylinders protrude up to the chip surface, so that an improved heat path from the semiconductor chip through the shaped elements into the metal layer is created. From the metal layer, the heat is dissipated through electrically non-connected solder points or solder balls, also known as no-connects, via so-called thermal vias in the printed circuit board in metal tracks on the printed circuit board.
  • thermal vias are, for example, metal-filled holes in the printed circuit board (circuit board), which are known using known methods, e.g. can be made by electroplating. If the shaped elements are arranged on the carrier layer in a corresponding number and corresponding surface area, a substantial improvement in the thermal resistance is achieved while the elastic or decoupling properties of the filling material are maintained.
  • a further embodiment of the invention provides a molded element applied to the metal layer, which is on a side of the carrier layer facing the semiconductor chip and is arranged laterally of the semiconductor chip. A further heat path is thus opened to the side of the semiconductor chip, which overall increases the thermal conductivity of the FBGA housing arrangement.
  • the mechanical stability of the housing arrangements described can be increased by a so-called support ring, i.e. a frame that surrounds the semiconductor chip.
  • a so-called support ring i.e. a frame that surrounds the semiconductor chip.
  • Such an application is useful, for example, for housing arrangements in which the solder joint array or the interposer protrudes beyond the chip area ("fan out").
  • the arrangement of this frame according to the invention thus provides the function of a heat sink in addition to the mechanically stabilizing function.
  • the frame is also electrically conductive and connected to ground potential, there are additional electrical improvements.
  • the frame which has the shape of a ring antenna with respect to the housing, provides a general shielding of all electrical paths of the metal layer.
  • the inductance of the ground connections connected to the frame is reduced, which above all reduces the noise as a result of rapid current changes (“delta-I noise”).
  • delta-I noise the noise as a result of rapid current changes
  • the capacity of the ground connections is increased, which leads to better high-frequency decoupling (“decoupimg”) of the voltage supply system.
  • decoupimg high-frequency decoupling
  • the inductance of further electrical connections for example of data lines or address lines, is also reduced by the additional ground reference that the frame represents.
  • the frame is applied directly to the metal layer and covered with a thermally conductive attached the glue. If the metal layer is on a side of the carrier layer opposite the frame, the frame is applied to the metal layer by a recess in the carrier layer via a conductive adhesive layer and is connected to it in a heat-conducting manner. This connection can also be made via a so-called bond.
  • an additional, electrically non-conductive, heat-conductive connection is arranged between the semiconductor chip and the shaped element in a development of the invention.
  • This heat-conductive connection can be made, for example, using a heat-conducting paste.
  • Semiconductor chip can be achieved by connecting wiring connections of the semiconductor chip to the metal layer of the interposer without an electrical function.
  • FIG. 3 shows a top view of an embodiment of the invention
  • FIG. 4 shows a three-dimensional representation of an embodiment of the invention
  • FIG. 5 shows a housing arrangement in a sectional illustration according to an embodiment of the invention
  • 6 and 7 each show a detailed illustration of FIG. 5
  • FIG. 8 shows a top view of an embodiment of the invention according to FIG. 5.
  • FIG. 1 shows a cross section of an FBGA housing arrangement with a structure according to an embodiment of the invention prior to assembly of the semiconductor chip.
  • the carrier layer 3 interposer
  • the metal layer 5 has a shaped element 7 made of heat-dissipating material, which is designed as a cylinder.
  • other cylinders of the same type are shown, which are formed, for example, from metal and which are thermally conductively connected to the metal layer.
  • the filler 4 (cushion material) is applied above the metal layer 5.
  • FIG. 2 shows a cross section of the structure according to FIG. 1 after the chip and solder ball assembly and after being soldered onto the printed circuit board 8.
  • the carrier layer 3 is arranged between the semiconductor chip 2 and the printed circuit board 8 and is used for rewiring wiring connections (so-called bond pads) of the semiconductor chip 2 onto the printed circuit board 8 by means of the printed conductor 13.
  • the carrier layer 3 is connected to the printed circuit board 8 via solder points 6.
  • the filler 4 is arranged between the semiconductor chip 2 and the carrier layer 3 and serves for the mechanical decoupling of the semiconductor chip 2 and the solder points 6.
  • the printed circuit board 8 is composed of the so-called Prmted Circuit Board (PCB) 81 and a large-area copper layer 82 (power plane of the PCB).
  • PCB Prmted Circuit Board
  • the filler 4 usually consists of a material based on poly id.
  • the carrier layer 3 consists, for example, of a carrier material FR-.
  • the power loss generated in the semiconductor chip 2 is dissipated via the metal layer 5 and the solder points 6 via the thermal via 9 shown in the printed circuit board 8, represented by the heat conduction path 20. Since the distance between the metal layer 5 and the semiconductor chip is via the shaped element 7 2 is reduced, the thermal conductivity along the heat conduction path 20 and thus the semiconductor device 1 is increased overall.
  • FIGS. 3 and 4 show a top view and a three-dimensional representation of the embodiment of the invention according to FIGS. 1 and 2.
  • the wiring connections 11 of the semiconductor chip 2 are connected to the solder points or solder balls 6 via the connections 61 for the solder points.
  • the connections 62 designate connections for "thermal", i.e. electrically inactive solder joints 6.
  • the metal layer 5 is arranged in the form of interconnected large metal surfaces.
  • the shaped elements 7 are applied to the metal layer 5 in a correspondingly dense surface coverage.
  • FIG. 5 shows a further housing arrangement in a sectional view.
  • the shaped element 7 is arranged on a side of the carrier layer 5 facing the semiconductor chip 2 and on the side of the semiconductor chip 2.
  • the shaped element 7 is designed in the form of a frame which surrounds the semiconductor chip 2.
  • the frame also contributes to the mechanical stabilization of the housing.
  • the sectional view according to FIG. 5 is shown in detail in FIGS. 6 and 7.
  • the shaped element 7 is applied to the metal layer 5, for example, using a thermally conductive adhesive.
  • a plurality of spacers 14 are arranged between the semiconductor chip 2 and the carrier layer 3.
  • the spacers 14 consist, for example, of an organic material containing silicone rubber.
  • the shaped element 7 or the frame is expediently formed from metal.
  • An additional thermally conductive connection 15 is arranged between the semiconductor chip 2 and the shaped element 7, for example in the form of a thermal paste, as shown in FIG.
  • the adhesive layer not shown in FIG. 6 or FIG. 7, can also be replaced by a bond.
  • the metal layer 5 is formed, for example, from copper.
  • FIG. 8 shows a top view of the embodiment of the invention according to FIG. 5 with conductor tracks 13 and the wiring connections 11.
  • the metal layer 5 is arranged in the form of coherent metal surfaces. To connect the formula element or the frame to ground potential, the metal layer 5 is correspondingly connected to ground connections (so-called ground pins) via solder balls (not shown in the figure).

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

L'invention concerne un ensemble boîtier d'un composant à semi-conducteur, qui comprend une puce de semi-conducteur (2), une plaquette à circuit imprimé (8), sur laquelle est placé le composant à semi-conducteur (1), et une couche support (3) qui est placée entre la puce de semi-conducteur (2) et la plaque à circuit imprimé (8) pour établir par déviation une liaison entre les connexions de câblage (11) de la puce de semi-conducteur (2) et la plaque à circuit imprimé (8). La couche support est reliée à la plaque à circuit imprimé (8) par l'intermédiaire de points de soudure (6), et une matière de remplissage (4) se trouvant entre la puce de semi-conducteur (2) et la couche support (3) sert au désaccouplement mécanique de la puce de semi-conducteur (2) et des points de soudure (6). Sur la couche support (3) est appliquée une couche de métal (5) qui est reliée aux points de soudure (6). Sur la couche métallique (5) est appliqué au moins un élément façonné (7) constitué d'un matériau évacuant la chaleur qui est relié de façon thermoconductrice à la couche de métal (5). Ainsi, le boîtier permet d'obtenir une meilleure conductibilité de la puissance dissipée à évacuer de la puce de semi-conducteur (2) intégrée, les caractéristiques mécaniques voulues pour l'ensemble boîtier étant maintenues.
EP00990529A 1999-12-14 2000-12-13 Ensemble boitier d'un composant a semi-conducteur Withdrawn EP1238426A2 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19960246A DE19960246A1 (de) 1999-12-14 1999-12-14 Gehäuseanordnung eines Halbleiterbausteins
DE19960246 1999-12-14
PCT/DE2000/004437 WO2001045166A2 (fr) 1999-12-14 2000-12-13 Ensemble boitier d'un composant a semi-conducteur

Publications (1)

Publication Number Publication Date
EP1238426A2 true EP1238426A2 (fr) 2002-09-11

Family

ID=7932606

Family Applications (1)

Application Number Title Priority Date Filing Date
EP00990529A Withdrawn EP1238426A2 (fr) 1999-12-14 2000-12-13 Ensemble boitier d'un composant a semi-conducteur

Country Status (4)

Country Link
US (1) US7208827B2 (fr)
EP (1) EP1238426A2 (fr)
DE (1) DE19960246A1 (fr)
WO (1) WO2001045166A2 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10216873A1 (de) * 2002-04-17 2003-11-13 Infineon Technologies Ag Kontaktierbare integrierte Schaltung und Verfahren zur Herstellung einer solchen Schaltung
JP4556174B2 (ja) * 2004-12-15 2010-10-06 日本電気株式会社 携帯端末機器及び放熱方法
JP5496445B2 (ja) * 2007-06-08 2014-05-21 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US8184440B2 (en) * 2009-05-01 2012-05-22 Abl Ip Holding Llc Electronic apparatus having an encapsulating layer within and outside of a molded frame overlying a connection arrangement on a circuit board

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3039355B2 (ja) * 1996-02-06 2000-05-08 ソニー株式会社 フィルム回路の製造方法
JPH08335653A (ja) * 1995-04-07 1996-12-17 Nitto Denko Corp 半導体装置およびその製法並びに上記半導体装置の製造に用いる半導体装置用テープキャリア
KR100201380B1 (ko) * 1995-11-15 1999-06-15 김규현 Bga 반도체 패키지의 열방출 구조
US5719440A (en) * 1995-12-19 1998-02-17 Micron Technology, Inc. Flip chip adaptor package for bare die
KR100192760B1 (ko) * 1996-02-29 1999-06-15 황인길 메탈 캐리어 프레임을 이용한 bag반도체 패키지의 제조방법 및 그반도체 패키지
JPH1065072A (ja) 1996-08-20 1998-03-06 Taiyo Yuden Co Ltd 放熱電極構造
JP2001267473A (ja) * 2000-03-17 2001-09-28 Hitachi Ltd 半導体装置およびその製造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO0145166A2 *

Also Published As

Publication number Publication date
US7208827B2 (en) 2007-04-24
WO2001045166A3 (fr) 2002-04-11
WO2001045166A2 (fr) 2001-06-21
DE19960246A1 (de) 2001-07-05
US20050040517A1 (en) 2005-02-24

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