Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
  • H10F39/80—Constructional details of image sensors
  • H10F39/804—Containers or encapsulations
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B81—MICROSTRUCTURAL TECHNOLOGY
  • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
  • B81B7/00—Microstructural systems ; Auxiliary parts of microstructural devices or systems
  • B81B7/0032—Packages or encapsulation
  • B81B7/0077—Other packages not provided for in groups B81B7/0035 - B81B7/0074
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B81—MICROSTRUCTURAL TECHNOLOGY
  • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
  • B81B7/00—Microstructural systems ; Auxiliary parts of microstructural devices or systems
  • B81B7/0032—Packages or encapsulation
  • B81B7/0067—Packages or encapsulation for controlling the passage of optical signals through the package
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B81—MICROSTRUCTURAL TECHNOLOGY
  • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
  • B81B7/00—Microstructural systems ; Auxiliary parts of microstructural devices or systems
  • B81B7/0032—Packages or encapsulation
  • B81B7/007—Interconnections between the MEMS and external electrical signals
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B81—MICROSTRUCTURAL TECHNOLOGY
  • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
  • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
  • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
  • B81C1/00261—Processes for packaging MEMS devices
  • B81C1/00301—Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
  • H03H9/00—Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators
  • H03H9/02—Details
  • H03H9/05—Holders or supports
  • H03H9/10—Mounting in enclosures
  • H03H9/1007—Mounting in enclosures for bulk acoustic wave [BAW] devices
  • H03H9/105—Mounting in enclosures for bulk acoustic wave [BAW] devices the enclosure being defined by a cover cap mounted on an element forming part of the BAW device
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
  • H03H9/00—Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators
  • H03H9/02—Details
  • H03H9/05—Holders or supports
  • H03H9/10—Mounting in enclosures
  • H03H9/1057—Mounting in enclosures for microelectro-mechanical devices
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
  • H03H9/00—Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators
  • H03H9/02—Details
  • H03H9/05—Holders or supports
  • H03H9/10—Mounting in enclosures
  • H03H9/1064—Mounting in enclosures for surface acoustic wave [SAW] devices
  • H03H9/1092—Mounting in enclosures for surface acoustic wave [SAW] devices the enclosure being defined by a cover cap mounted on an element forming part of the surface acoustic wave [SAW] device on the side of the IDT's
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
  • H10F39/011—Manufacture or treatment of image sensors covered by group H10F39/12
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
  • H10W76/60—Seals
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W95/00—Packaging processes not covered by the other groups of this subclass
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B81—MICROSTRUCTURAL TECHNOLOGY
  • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
  • B81B2207/00—Microstructural systems or auxiliary parts thereof
  • B81B2207/09—Packages
  • B81B2207/091—Arrangements for connecting external electrical signals to mechanical structures inside the package
  • B81B2207/097—Interconnects arranged on the substrate or the lid, and covered by the package seal
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B81—MICROSTRUCTURAL TECHNOLOGY
  • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
  • B81C2203/00—Forming microstructural systems
  • B81C2203/01—Packaging MEMS
  • B81C2203/0118—Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B81—MICROSTRUCTURAL TECHNOLOGY
  • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
  • B81C2203/00—Forming microstructural systems
  • B81C2203/03—Bonding two components
  • B81C2203/032—Gluing
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/01—Manufacture or treatment
  • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/01—Manufacture or treatment
  • H10W72/0198—Manufacture or treatment batch processes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps

Definitions

• Wire bonding employs heat and ultrasonic energy to weld gold bonding wires between bond pads on the chip and contacts on the package
• T.AB Tape automatic bonding
• the copper foil tape is configured for each specific die and package combination and includes a pattern of copper traces suited thereto
• the individual leads may be connected individually or as a group to the various bond pads on the chip
• the flip-chip does not provide packaging but rather only interconnection
• the interconnection encounters problems of uniformity in the solder bumps as well as in thermal expansion mismatching, which limits the use of available substrates to silicon or materials which have thermal expansion characteristics similar to those of silicon.
• the present invention seeks to provide improved packaged crystalline substrate based devices and methods for producing same.
• a crystalline substrate based device including a crystalline substrate having formed thereon a microstructure and at least one packaging layer which is sealed over the microstructure by an adhesive and defines therewith at least one gap between the crystalline substrate and the at least one packaging layer.
• chip scale packaged crystalline substrate including: a substrate having formed thereon a microstructure; and at least one chip scale package which is sealed over the microstructure and defines therewith at least one gap.
• a method of producing a crystalline substrate based device including: providing a microstructure on a substrate; and adhesively sealing at least one packaging layer over the microstructure and at least partially spaced therefrom, thereby to define a gap between the microstructure and the at least one packaging layer.
• At least one packaging layer is sealed onto the crystalline substrate using an adhesive, such as epoxy.
• the crystalline substrate includes silicon, lithium niobate, lithium tantalate or quartz.
• the at leas: one packaging layer is transparent.
• the at least one cavity may include a single cavity or a plurality of cavities.
• the microstructure may include a micromechanical structure, a microelectronic structure and/or an optoelectronic structure.
• Figs. 1A and IB are pictorial illustrations of a crystalline substrate based device having an internal cavity, constructed and operative in accordance with a preferred embodiment of the present invention
• Figs. 2A, 2B, 2C & 2D are simplified sectional illustrations of various crystalline substrate based devices constructed and operative in accordance with a preferred embodiment of the present invention, corresponding generally to Figs. 1A and IB;
• Fig. 3 is a partially cut-away sectional illustration of a crystalline substrate based device of the type shown in Figs. 1 A & IB;
• FIGs. 4A, 4B, 4C, 4D & 4E are simplified illustrations of steps in a method for producing a packaging layer for use in crystalline substrate based device in accordance with a preferred embodiment of the present invention
• Figs. 5A, 5B, 5C, 5D, 5E, 5F, 5G, 5H & 51 are simplified illustrations of steps in a method for producing a crystalline substrate based device of the type shown in Figs. 2A & 2C in accordance with a preferred embodiment of the present invention
• Figs. 6A, 6B, 6C, 6D, 6E, 6F, 6G, 6H, 61, 6J & 6K are simplified illustrations of steps in a method for producing a crystalline substrate based device of the type shown in Fig. 2B in accordance with another preferred embodiment of the present invention
• Figs. 7A, 7B, 7C, 7D, 7E, 7F & 7G are simplified illustrations of steps in a method for producing a crystalline substrate based device of the type shown in Fig. 2D in accordance with another preferred embodiment of the present invention
• Figs. 8A and 8B are illustrations of apparatus typically employed in the manufacture of a crystalline substrate based devices of the type shown in Figs. 2A & 2C in the manner shown in Figs. 5A - 51;
• Figs. 9A and 9B are illustrations of apparatus typically employed in the manufacture of a crystalline substrate based devices of the type shown in Fig. 2B in the manner shown in Figs. 6A - 6K;
• Figs. 10A and 10B are illustrations of apparatus typically employed in the manufacture of a crystalline substrate based devices of the type shown in Fig. 2D in the manner shown in Figs. 7A - 7G.
• the integrated circuit device includes a relatively thin and compact, environmentally protected and mechanically strengthened integrated circuit package 10 having a multiplicity of electrical contacts 12 plated along the edge surfaces 14 thereof.
• contacts 12 extend over edge surfaces onto the planar surfaces 16 of the package.
• This contact arrangement permits both flat surface mounting and edge mounting of package 10 onto a circuit board.
• the integrated circuit package 10 may include one or more of the following elements (not shown): an integrally formed dichroic filter, color filter, ant i reflective coating, polarizer, optical grating, integrated wave guide and optical coupling bumps.
• the integrated circuit package 10 defines a cavity 18, which is indicated in phantom lines.
• FIGs. 2A - 2D illustrate four alternative preferred embodiments of integrated circuit devices of the general type shown in Figs. 1A & IB, constructed and operative in accordance with another preferred embodiment of the present invention.
• Each of the devices shown in Figs. 2A - 2D includes a relatively thin and compact, environmentally protected and mechanically strengthened integrated circuit package having a multiplicity of electrical contacts plated along the edge surfaces thereof.
• Fig. 2A shows an integrated circuit device including a microlens array 100 formed on a crystalline substrate 102.
• a packaging layer 106 typically formed of glass, along edges of which are formed electrical contacts 108, typically defining bumps 110.
• Conductive pads 112 preferably connect substrate 102 to electrical contacts 108.
• a packaging layer 114 typically formed of glass, and associated spacer elements 116, are sealed, by means of an adhesive such as epoxy 1 18, over substrate 102 so as to define a cavity 120 between the microlens array 100 and layer 1 14
• packaging layer 1 14 is preferably transparent and may have formed thereon a dichroic filter and/or anti-reflective coating.
• Fig. 2B show s an integrated circuit device including an optoelectronic or electromechanical device 150, such as a chemical sensor, a micromirror array or an accelerometer is suspended on a crystalline substrate 152, as by an electrically conductive connector 154 Sealed onto substrate 152 is a packaging layer 156 typically formed of glass, along edges of which are formed electrical contacts 158, typically defining bumps 160 Conductive pads 162 preferably connect substrate 152 to electrical contacts 158
• a packaging layer 164 typically formed of glass, and associated spacer elements 166, are sealed, by means of an adhesive, such as epoxy 168, over substrate 152 so as to define first and second cavities 170 and 172 between the device 150 and both layer 164 and layer 156
• packaging layer 164 is preferably transparent and may have formed thereon a dichroic filter and/or anti-reflective coating.
• Fig. 2C shows an integrated circuit device including a optoelectronic or electromechanical device 200 formed on a crystalline substrate 202. Underlying the substrate 202 and sealed thereto by epoxy 204 is a packaging layer 206, typically formed of glass, along edges of which are formed electrical contacts 208, typically defining bumps 210 Conductive pads 212 preferably connect substrate 202 to electrical contacts 208
• a packaging layer 214 typically formed of glass, and associated spacer elements 216, are sealed, by means of an adhesive such as epoxy 218, over substrate 202 so as to define a cavity 220 between the device 200 and layer 214
• packaging layer 214 is preferably transparent and may have formed thereon a dichroic filter and/or anti-reflective coating.
• Fig. 2D shows a Surface Acoustic Wave (SAW) device including a SAW propagation surface 250 defined on a crystalline substrate 252, along edges of which are formed electrical contacts 258, typically defining bumps 260. Conductive pads 262 preferably connect substrate 252 to electrical contacts 258.
• SAW Surface Acoustic Wave
• a packaging layer 264 typically formed of glass, and associated spacer elements 266, are sealed, by means of an adhesive such as epoxy 268, over substrate 252 so as to define a cavity 270 between surface 250 and layer 264.
• FIG. 3 is a partially cut away illustration of a typical integrated circuit device of the type shown in Figs. 1A - 2D, having a cavity as indicated by reference numeral 280.
• Figs. 4A, 4B, 4C, 4D & 4E are simplified illustrations of steps in a method for producing a packaging layer for use in crystalline substrate based device in accordance with a preferred embodiment of the present invention.
• a substrate 300 typically formed of glass, is preferably coated with a layer 302 of epoxy based photoresist, typically SU-8 photoresist, commercially available from MicroChem Corp. of Newton, MA, USA.
• the photoresist layer 302 is exposed via a mask 304, as shown in Fig. 4C and washed to define spacers 306 shown in Fig. 4D, which are typically of rectangular configuration, as indicated in Fig. 4E. These spacers correspond to spacer elements 1 16, 166, 216 and 266 in Figs. 2A - 2D respectively.
• FIGs. 5A, 5B, 5C, 5D, 5E, 5F, 5G, 5H & 51 are simplified illustrations of steps in a method for producing a crystalline substrate based device of the type shown in Figs. 2A & 2C in accordance with a preferred embodiment of the present invention.
• a packaging layer 400 typically of the type shown in Figs. 4D and 4E is provided.
• Adhesive 402 is applied thereto, preferably adjacent and between spacers 406 formed thereon, which correspond to the spacers 306 shown in Figs. 4D & 4E respectively and also correspond to spacer elements 1 16, 166, 216 and 266 in Figs. 2A - 2D respectively.
• Adhesive 402 is preferably a high temperature epoxy, such as EPO-TEK 353ND, commercially available from Epoxy Technology Inc. of Billerica, MA, USA.
• the packaging layer 400 As shown in Fig. 5B, the packaging layer 400, thus prepared, is adhered to a crystalline substrate 404, typ cally having at least one metal layer thereon and having mounted thereon optomechanical or optoelectronic devices of the types described hereinabove with reference to Figs. 2A & 2C. As seen clearly, a cavity 405 is defined between the packaging layer 400 and the substrate 404, in accordance with a preferred embodiment of the present invention.
• the crystalline substrate 404 is preferably lapped, as shown in Fig. 5C and etched, as shown in Fig. 5D, to define separate substrates 407. Following etching, the substrates 407 are adhered via an epoxy layer 408 to an underlying packaging layer 410, as shown in Fig. 5E.
• the packaging layer 410 and epoxy layer 408 are mechanically notched and thereafter electrical contacts 412 and typically bumps 414 are formed thereon, as seen in Fig. 5G.
• the resulting assembly is diced as shown in Fig. 5H to yield a plurality of packaged integrated circuit devices, as seen in Fig. 51.
• the crystalline substrate may be any suitable crystalline substrate and may comprise, for example, silicon, lithium niobate, lithium tantalate or quartz.
• FIGs. 6A, 6B, 6C, 6D, 6E, 6F, 6G, 6H, 61, 6J & 6K are simplified illustrations of steps in a method for producing a crystalline substrate based device of the type shown in Fig. 2B in accordance with another preferred embodiment of the present invention.
• a substrate 500 mounted on a substrate 500, typically formed of Pyrex are a plurality of crystalline substrates 502 onto which are formed pads 504 and onto which are suspended, as by electrically conductive connectors 506, optoelectronic or electromechanical devices 508, such as chemical sensors, micromirror arrays or an accelerometer, which may correspond to devices 150 of the type shown in Fig. 2B.
• a substrate 500 typically formed of Pyrex are a plurality of crystalline substrates 502 onto which are formed pads 504 and onto which are suspended, as by electrically conductive connectors 506, optoelectronic or electromechanical devices 508, such as chemical sensors, micromirror arrays or an accelerometer, which may correspond to devices 150 of the type shown in Fig. 2B.
• a packaging layer 510 typically of the type shown in Figs. 4D and 4E, is provided having adhesive 512 applied thereto, preferably adjacent and between spacers 516 formed thereon, which correspond to the spacers 306 shown in Figs. 4D & 4E respectively and also correspond to spacer elements 116, 166, 216 and 266 in Figs. 2A - 2D respectively.
• Adhesive 512 is preferably a high temperature epoxy, such as EPO-TEK 353ND, commercially available from Epoxy Technology Inc. of Billerica, MA, USA.
• the packaging layer 510 As seen in Fig. 6C, the packaging layer 510, thus prepared, is adhered to crystalline substrates 502, typically adjacent pads 504. As seen clearly, a cavity 513 is defined between the packaging layer 510 and the substrates 502, and another cavity 514 is defined between substrates 502, substrate 500 and electromechanical devices 508 in accordance with a preferred embodiment of the present invention.
• the substrate 500 and crystalline substrates 502 are preferably notched, as shown in Fig. 6D and etched, as shown in Fig. 6E, to define volumes 515 in crystalline substrates 502 which are preferably filled with epoxy 517, as shown in Fig. 6F.
• the substrate 500, the epoxy 516 and the adhesive 512 are then mechanically notched to form a notch 501, and thereafter electrical contacts 519 are formed thereon, as by sputtering, as shown in Fig. 6H.
• Bumps 518 are formed thereon, as seen in Fig. 61, preferably together with a NiAu coating.
• the resulting assembly is diced as shown in Fig. 6J to yield a plurality of packaged integrated circuit devices, as seen in Fig. 6K.
• FIGs. 7A, 7B, 7C, 7D, 7E, 7F & 7G are simplified illustrations of steps in a method for producing a crystalline substrate based device of the type shown in Fig. 2D in accordance with another preferred embodiment of the present invention.
• a packaging layer 600 typically of the type shown in Figs. 4D and 4E is provided.
• Adhesive 602 is applied thereto, preferably adjacent and between spacers 606 formed thereon, which correspond to the spacers 306 shown in Figs. 4D & 4E respectively and also correspond to spacer elements 1 16, 166, 216 and 266 in Figs. 2A - 2D respectively.
• Adhesive 602 is preferably a high temperature epoxy, such as EPO-TEK 353ND, commercially available from Epoxy Technology Inc. of Billerica, MA, USA.
• the packaging layer 600 As shown in Fig. 7B, the packaging layer 600, thus prepared, is adhered to a crystalline substrate 604, typically having at least one metal layer thereon and having defined thereon a SAW propagation layer 609 as described hereinabove with reference to Fig. 2D. As seen clearly, a cavity 607 is defined between the packaging layer 600 and the SAW propagation layer 609, in accordance with a preferred embodiment of the present invention.
• the crystalline substrate 604 can be lapped, as shown in Fig. 7C and notched partially into the adhesive 602, as shown in Fig. 7D, to define separate substrates 608. Following etching, electrical contacts 610 and typically bumps 614 are formed thereon, as seen in Fig. 7E. The resulting assembly is diced as shown in Fig. 7F to yield a plurality of packaged SAW devices, as seen in Fig. 7G.
• Figs. 8A and 8B are illustrations of apparatus employed in the manufacture of a crystalline substrate based devices of the type shown in Figs. 2A & 2C in the manner shown in Figs. 5A - 51.
• a conventional wafer fabrication facility 680 provides complete wafers 681, of the type shown in Fig. 5A.
• Individual wafers 682 are bonded on their active surfaces to protective layers 683 as shown in Figs. 5A & 5B, by bonding apparatus 685, preferably having facilities for rotation of the wafer 682, the layer 683 and the epoxy so as to obtain even distribution of the epoxy.
• the bonded wafer 686 is thinned (Fig. 5C) at its non-active surface as by grinding apparatus 684, such as Model 32BTGW using 12.5A abrasive 687, which is commercially available from Speedfam Machines Co. Ltd. of England.
• the wafer is then etched (Fig. 5D) at its non-active surface, preferably by photolithography, such as by using conventional spin-coated photoresist, which is commercially available from Hoechst, under the brand designation AZ 4562, using a mask exposure machine 692 for the exposure of light sensitive photoresist 690 through the mask 691 and later etching the silicon in a bath 693 using solution 699.
• photolithography such as by using conventional spin-coated photoresist, which is commercially available from Hoechst, under the brand designation AZ 4562
• the etched wafer 1000 is bonded (Fig. 5E) on the non-active side to protective layer 686 by bonding apparatus 694, which may be essentially the same as apparatus 685, to produce a doubly bonded wafer sandwich.
• Notching apparatus 695 partially cuts the bonded wafer sandwich of Fig. 5E to the configuration shown in Fig. 5F
• the notched wafer 1002 is then preferably subjected to anti-corrosion treatment in a bath 696, containing a chromating solution 698, such as described in any of the following U.S. Patents: 2,507,956; 2,851,385 and 2,796,370, the disclosure of which is hereby incorporated by reference.
• Conductive layer deposition apparatus 700 which operates by vacuum deposition techniques, such as a Model 903M sputtering machine manufactured by Material Research Corporation of the U.S.A., is employed to produce a conductive layer on one or more surfaces of each die of the wafer as shown in Fig. 5G.
• Configuration of contact strips is carried out preferably by using conventional electro-deposited photoresist 701, which is commercially available from DuPont under the brand name Primecoat or from Shipley, under the brand name Eagle.
• the photoresist 701 is applied to the wafers 707 in a photoresist bath assembly 702, which is commercially available from DuPont or Shipley.
• the photoresist 703 is preferably light configured by a UV exposure system 704, which may be identical to system 692, using a mask 705 to define suitable etching patterns.
• the photoresist is then developed in a development bath 706, and then the wafer is etched in a metal etch solution 708 located in an etching bath 710, thus providing a conductor configuration such as that shown in Fig. 5G.
• the exposed conductive strips shown in Fig. 5G are then plated, preferably by electroless plating apparatus 712, which is commercially available from Okuno of Japan.
• the wafer is then diced (Fig. 5H) into individual pre-packaged integrated circuit devices.
• the dicing blade 714 should be a diamond resinoid blade of thickness 4 - 12 mils.
• the resulting dies appear as illustrated generally in Fig. 51.
• Figs. 9A and 9B are illustrations apparatus employed in the manufacture of a crystalline substrate based devices of the type shown in- Fig. 2B in the manner shown in Figs. 6A - 6K.
• a wafer fabrication facility 780 provides complete wafers 781, of the type shown in Fig. 6A mounted onto a substrate, such as a Pyrex substrate 782.
• Individual wafers 781 are bonded on their active surfaces to protective layers 783 as shown in Figs. 6B & 6C, by bonding apparatus 784, preferably having facilities for rotation of the wafer 781, the layer 783 and the epoxy so as to obtain even distribution of the epoxy.
• Notching apparatus 794 partially cuts the bonded wafer sandwich 793 of Fig. 6C to the configuration shown in Fig. 6D.
• the notched wafer 796 is then etched in a silicon etching solution 798 in a bath 1010.
• the etched voids 1012 in wafer 1014 are filled with epoxy 1016, using a dispenser 1018 to fill the voids 1012, to obtain epoxy filled voids 1020.
• the wafer 1022 is notched again using apparatus 1024 through the epoxy filled trenches 1020
• the notched wafer 1028 is then preferably subjected to anti-corrosion treatment in a bath 1030, containing a chromating solution 1032, such as described in any of the following U S Patents 2,507,956, 2,851,385 and 2,796,370, the disclosure of which is hereby incorporated by reference
• Conductive layer deposition apparatus 800 which operates by vacuum deposition techniques, such as a Model 903M sputtering machine manufactured by Material Research Corporation of the U S A , is employed to produce a conductive layer on one or more surfaces of each die of the wafer as shown in Fig. 6G.
• Configuration of contact strips is carried out preferably by using conventional electro-deposited photoresist 801, which is commercially available from DuPont under the brand name Primecoat or from Shipley, under the brand name Eagle.
• the photoresist is applied to the wafers 803 in a photoresist bath assembly 802, which is commercially available from DuPont or Shipley
• the photoresist 807 is preferably light configured by a UV exposure system 804 using a mask 805 to define suitable etching patterns
• the photoresist is then developed in a development bath 806, and then etched in a metal etch solution 808 located in an etching bath 810, thus providing a conductor configuration such as that shown in Fig. IB.
• the exposed conductive strips shown in Fig 6G are then plated, preferably by electroless plating apparatus 812, which is commercially available from Okuno of Japan.
• the wafer is then diced (Fig 6H) into individual pre-packaged integrated circuit devices.
• the dicing blade 814 should be a diamond resinoid blade of thickness 4 - 12 mils
• the resulting dies appear as illustrated generally in Fig. 6K.
• Figs 10A and 10B are illustrations apparatus employed in the manufacture of a crystal line substrate based device of the type shown in Fig. 2D in the manner shown in Figs 7A - 7G
• a conventional wafer fabrication facility 880 provides complete wafers 881, of the type shown in Fig. 7A.
• Individual wafers 881 are bonded on their active surfaces to protective layers 883 as shown in Figs 7A & 7B, by bonding apparatus 882, preferably having facilities for rotation of the wafer 881, the layer 883 and the epoxy so as to obtain even distribution of the epoxy
• Notching apparatus 894 partially cuts the wafer 883 of Fig. 7E to the configuration shown in Fig. 7F
• the notched wafer 884 is then preferably subjected to anti-corrosion treatment in a bath 896, containing a chromating solution 898, such as described in any of the following U S. Patents 2,507,956, 2,851,385 and 2,796,370, the disclosure of which is hereby incorporated by reference
• Conductive layer deposition apparatus 900 which operates by vacuum deposition techniques, such as a Model 903M sputtering machine manufactured by Material Research Corporation of the U S A., is employed to produce a conductive layer on one or more surfaces of each die of the wafer as shown in Fig. 7G.
• Configuration of contact strips is carried out preferably by using conventional electro-deposited photoresist 901, which is commercially available from DuPont under the brand name Primecoat or from Shipley, under the brand name Eagle.
• the photoresist 901 is applied to the wafers 903 in a photoresist bath assembly 902, which is commercially available from DuPont or Shipley
• the photoresist 920 is preferably light configured by a UV exposure system 904 using a mask 905 to define suitable etching patterns
• the photoresist is then developed in a development bath 906, and then etched in a metal etch solution 908 located in an etching bath 910, thus providing a conductor configuration such as that shown in Fig. IB
• the exposed conductive strips shown in Fig 7G are then plated, preferably by electroless plating apparatus 912, which is commercially available from Okuno of Japan.
• the wafer 913 is then diced (Fig. 5H) into individual pre-packaged integrated circuit devices.
• the dicing blade 914 should be a diamond resinoid blade of thickness 4 - 12 mils
• the resulting dies appear as illustrated generally in Fig 7G

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• Computer Hardware Design (AREA)
• Manufacturing & Machinery (AREA)
• Micromachines (AREA)
• Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)

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• 1999
  • 1999-12-10 IL IL13345399A patent/IL133453A0/xx unknown
• 2000
  • 2000-11-26 KR KR1020027007284A patent/KR100725107B1/ko not_active Expired - Lifetime
  • 2000-11-26 CN CNB00816990XA patent/CN1222024C/zh not_active Expired - Lifetime
  • 2000-11-26 WO PCT/IL2000/000786 patent/WO2001043181A1/en not_active Ceased
  • 2000-11-26 CA CA002394458A patent/CA2394458A1/en not_active Abandoned
  • 2000-11-26 EP EP00979896.8A patent/EP1247293B1/de not_active Expired - Lifetime
  • 2000-11-26 AU AU17272/01A patent/AU1727201A/en not_active Abandoned
  • 2000-11-26 JP JP2001543771A patent/JP5160710B2/ja not_active Expired - Lifetime
  • 2000-11-28 TW TW089125196A patent/TW466722B/zh not_active IP Right Cessation
  • 2000-11-29 US US09/725,166 patent/US6777767B2/en not_active Expired - Lifetime
• 2001
  • 2001-08-07 US US09/922,770 patent/US7144745B2/en not_active Expired - Lifetime
• 2006
  • 2006-10-26 US US11/588,489 patent/US7939918B2/en not_active Expired - Fee Related

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