FR3142832B1 - Procede de fabrication de plusieurs boitiers de circuits integres - Google Patents

Procede de fabrication de plusieurs boitiers de circuits integres Download PDF

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Publication number
FR3142832B1
FR3142832B1 FR2212804A FR2212804A FR3142832B1 FR 3142832 B1 FR3142832 B1 FR 3142832B1 FR 2212804 A FR2212804 A FR 2212804A FR 2212804 A FR2212804 A FR 2212804A FR 3142832 B1 FR3142832 B1 FR 3142832B1
Authority
FR
France
Prior art keywords
face
zci
fext
res
sub
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR2212804A
Other languages
English (en)
Other versions
FR3142832A1 (fr
Inventor
Laurent Herard
Olivier Zanellato
Patrick Laurent
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics International NV Switzerland
STMicroelectronics International NV
Original Assignee
STMicroelectronics International NV Switzerland
STMicroelectronics International NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics International NV Switzerland, STMicroelectronics International NV filed Critical STMicroelectronics International NV Switzerland
Priority to FR2212804A priority Critical patent/FR3142832B1/fr
Priority to US18/529,064 priority patent/US20240186195A1/en
Priority to CN202323324787.0U priority patent/CN222106674U/zh
Priority to CN202311668439.7A priority patent/CN118156146A/zh
Publication of FR3142832A1 publication Critical patent/FR3142832A1/fr
Application granted granted Critical
Publication of FR3142832B1 publication Critical patent/FR3142832B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00—Cutting or separating of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/10—Containers or parts thereof
    • H10W76/12—Containers or parts thereof characterised by their shape
    • H10W76/15—Containers comprising an insulating or insulated base
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/60—Seals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W95/00—Packaging processes not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Engineering & Computer Science (AREA)
  • Ceramic Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

Selon un aspect, il est proposé un boîtier de circuits intégrés (BT) comportant un substrat support (SUB) possédant une face de montage (FM), une paroi latérale (RES) ayant une face interne (FINT) et une face externe (FEXT), la face interne (FINT) délimitant avec la face de montage (FM) une cavité (ZCI), la face externe (FEXT) comportant une marche (STP) s’étendant vers l’extérieur du boîtier (BT), une puce électronique (CHP) disposée dans la cavité (ZCI) et électriquement connectée à des plages de contact électriquement conductrices (PAD), un moyen d’obturation (CAP), collé au moyen d’une colle (GL2), sur une face supérieure (FH) de la paroi latérale (RES) et obturant la cavité (ZCI), ladite colle (GL2) ne débordant pas sur la face externe (FEXT) de la paroi latérale (RES), et des moyens de connexion électriquement conducteurs (BP) situés sur une face inférieure (FL) du substrat support (SUB) et en coopération électrique avec lesdites plages de contact (PAD) par l’intermédiaire d’un réseau d’interconnexion (INTCNX) situé dans le substrat support (SUB). Figure pour l’abrégé : Fig 6
FR2212804A 2022-12-06 2022-12-06 Procede de fabrication de plusieurs boitiers de circuits integres Active FR3142832B1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
FR2212804A FR3142832B1 (fr) 2022-12-06 2022-12-06 Procede de fabrication de plusieurs boitiers de circuits integres
US18/529,064 US20240186195A1 (en) 2022-12-06 2023-12-05 Method for manufacturing several integrated circuit packages
CN202323324787.0U CN222106674U (zh) 2022-12-06 2023-12-06 一种集成电路包装
CN202311668439.7A CN118156146A (zh) 2022-12-06 2023-12-06 制造若干集成电路包装的方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR2212804 2022-12-06
FR2212804A FR3142832B1 (fr) 2022-12-06 2022-12-06 Procede de fabrication de plusieurs boitiers de circuits integres

Publications (2)

Publication Number Publication Date
FR3142832A1 FR3142832A1 (fr) 2024-06-07
FR3142832B1 true FR3142832B1 (fr) 2024-12-13

Family

ID=86764605

Family Applications (1)

Application Number Title Priority Date Filing Date
FR2212804A Active FR3142832B1 (fr) 2022-12-06 2022-12-06 Procede de fabrication de plusieurs boitiers de circuits integres

Country Status (3)

Country Link
US (1) US20240186195A1 (fr)
CN (2) CN118156146A (fr)
FR (1) FR3142832B1 (fr)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IL133453A0 (en) * 1999-12-10 2001-04-30 Shellcase Ltd Methods for producing packaged integrated circuit devices and packaged integrated circuit devices produced thereby
US7187077B1 (en) * 2004-03-19 2007-03-06 Xilinx, Inc. Integrated circuit having a lid and method of employing a lid on an integrated circuit
US7936062B2 (en) * 2006-01-23 2011-05-03 Tessera Technologies Ireland Limited Wafer level chip packaging
WO2013076830A1 (fr) * 2011-11-22 2013-05-30 富士通株式会社 Composant électronique et procédé de production de celui-ci
CN105632911A (zh) * 2016-01-02 2016-06-01 北京工业大学 降低边缘应力的晶圆级封装方法

Also Published As

Publication number Publication date
FR3142832A1 (fr) 2024-06-07
US20240186195A1 (en) 2024-06-06
CN222106674U (zh) 2024-12-03
CN118156146A (zh) 2024-06-07

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