EP1248953A1 - Carte imprimee equipee, munie de chemins de balayage peripherique configurables - Google Patents

Carte imprimee equipee, munie de chemins de balayage peripherique configurables

Info

Publication number
EP1248953A1
EP1248953A1 EP01904832A EP01904832A EP1248953A1 EP 1248953 A1 EP1248953 A1 EP 1248953A1 EP 01904832 A EP01904832 A EP 01904832A EP 01904832 A EP01904832 A EP 01904832A EP 1248953 A1 EP1248953 A1 EP 1248953A1
Authority
EP
European Patent Office
Prior art keywords
test
boundary scan
printed circuit
circuit assembly
recited
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP01904832A
Other languages
German (de)
English (en)
Inventor
Han Y. Ko
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sun Microsystems Inc
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Publication of EP1248953A1 publication Critical patent/EP1248953A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
    • G01R31/281—Specific types of tests or tests for a specific type of fault, e.g. thermal mapping, shorts testing
    • G01R31/2815—Functional tests, e.g. boundary scans, using the normal I/O contacts

Definitions

  • TITLE A PRINTED CIRCUIT ASSEMBLY WITH CONFIGURABLE BOUNDARY SCAN PATHS
  • This invention relates to the testing of electronic circuits, and more specifically, the use of boundary scan for testing p ⁇ nted circuit assemblies
  • Boundary scan is one solution to testing integrated circuits with large gate and pm counts As the gate and pm counts of integrated circuits has grown, device-level testing of integrated circuits on printed circuit assemblies (PCA's) has become increasingly difficult, and in many cases is no longer practical Device-level testing involves driving logic stimuli to the inputs of a device, and monitoring the resulting outputs Such testing may require the generation of a very large number of test vectors Despite the difficulty of device-level testing, the need persists for ensuring that the correct devices are mounted upon a printed circuit board in the correct orientation with good solder connections Boundary scan may provide a solution to this problem
  • Boundary scan testing occurs at the boundary between the core logic of a device and its external pm connections
  • a device configured for boundary scan typically includes boundary scan cells, each of which is located between a signal pm and the core logic of the device
  • a plurality of these boundary scan cells may be connected together to form a boundary scan chain, or path Figure 1 is an illustration of an exemplary integrated circuit (IC) configured for boundary scan testing
  • the IC includes a plurality of boundary scan cells chained together During normal IC operations, data may pass unaffected through the boundary scan cells between the core logic and signal pms
  • test data may enter the IC through the TDI (Test Data In) pin, and pass through the chain of boundary scan cells, leaving the chip through the TDO (Test Data Out) pm
  • the chain of boundary scan cells acts as a shift register, as data bits may be shifted from one cell to the next
  • the state of each boundary scan cell may be monitored during scan shifting through those signal pms associated with an output or bi-directional signal
  • TDI Transmission Data In
  • FIG. 2 is a block diagram ot a smgle scan path
  • a plurality of boundary scan IC"s are chamed together by coupling TDO outputs to TDI inputs
  • a TMS (Test Mode Select) signal is used to place the chips m a test mode, while the TCK (Test Clock) provides the necessary clock signal for shifting data through the scan chain
  • FIG. 3 The configuration shown includes two separate single scan paths, each with its own set of test signals (TDI and TDO) and control signals (TMS and TCK) These scan paths may be tested either sequentially or simultaneously
  • FIG. 4 Another popular configuration is parallel shared scan paths, as shown in Figure 4 In this configuration, two separate scan paths share TDI and TDO signal connections Each path has its own TMS and TCK signals Because of the shared TDI and TDO signals, only one scan path may be tested at a given time In general, a large number of scan path configurations are possible, and each configuration provides certain advantages and disadvantages Some configurations may be easier to implement during the design of a printed circuit assembly, but result in greater difficulty m generating test vectors Other configurations may provide simpler test solutions, but result in longer test times or lower test coverage
  • a PCA printed circuit assembly
  • a PCA is designed with a plurality of boundary scan paths, and these paths may be of different configurations Switches are mounted upon the printed circuit assembly m such a manner as to allow the boundary scan paths to be connected together These switches may be used to configure the multiple boundary scan paths into a single common boundary scan path
  • ATE automated test equipment
  • the tester may drive control signals to the UUT (Unit Under Test, l e the PCA being tested) for the purposes of configuring the boundary scan path
  • the boundary-scan test may be run
  • the switches used to configure the boundary scan paths may take on various forms In one embodiment, a plurality of 2-to-l multiplexers and l-to-2 de-multiplexers may be used to configure the boundary scan paths In other embodiments, various other types of switches may be used Control of the switch may be provided by the ATE during testing
  • the configurable boundary scan paths may provide greater flexibility in creating boundary scan test solutions for a PCA upon which they are implemented Since multiple scan path configurations are available, a test engineer may choose among a number of test solutions which enable the greatest test coverage Such test solutions may be easier to implement than those for non-configurable boundary scan paths
  • Figure 1 is a block diagram of an exemplary integrated circuit configured for boundary scan testing
  • Figure 2 (prior art) is a block diagram of a single scan path configuration
  • Figure 3 is a block diagram of a multiple independent scan path configuration
  • Figure 4 is a block diagram of a parallel shared scan path configuration
  • Figure 5 is a drawing of one embodiment of an m-circuit test system upon which boundary scan tests may be performed
  • Figure 6 is a drawing of a printed circuit assembly of one embodiment including two independent scan paths with switches for reconfiguring the paths,
  • Figure 7 is a block diagram illustrating an embodiment using switches to configure two multiple independent scan paths into a common scan path
  • FIG. 8 is a block diagram illustrating an embodiment using switches to configure two parallel shared scan paths into a common scan path While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example m the drawings and will herein be described m detail It should be understood, however, that the drawings and description thereto are not intended to limit the invention to the particular form disclosed, but, on the contrary, the invention is to cover all modifications, equivalents, and alternatives falling with the spirit and scoped of the present invention as defined be the appended claims
  • ICT system 100 upon which a printed circuit assembly with configurable boundary scan paths is tested is shown
  • ICT system 100 includes an instrument bay 101 and a test fixture 102
  • a fixture interface 103 at the top of instrument bay 101 is configured to electrically couple test fixture 102 to instrument bay 101
  • Test fixture 102 includes a plurality of test probes 104 configured to make electrical contact with test points located on printed circuit assembly 200
  • Test probes 104 are electrically coupled to fixture interface 103 through fixture wires 105, which are typically arranged as twisted pairs
  • a retainer 106 is configured to secure printed circuit assembly 200 m place during testing
  • instrument bay 101 is configured to drive test signals to printed circuit assembly 200 through fixture interface 103, fixture wires 105, and test probes 104 Instrument bay 101 may also receive response signals from printed circuit assembly 200
  • Signals driven to p ⁇ nted circuit assembly (PCA) 200 from instrument bay 101 may include analog and/or digital signals
  • instrument bay 101 may drive digital signals for boundary scan testing to a test-data m (TDI) node on a PCA, and receive signals from a test-data out (TDO) node of the PCA Instrument bay 101 is configured to determine the pass/fail status for a given test of a PCA Instrument bay 101 is also configured to drive control signals to the PCA under test, such as the TMS (Test Mode Select) and TCK (Test Clock) signals that may be required for boundary scan testing
  • instrument bay 101 may drive control signals for switch positioning to a PCA having switches for connecting boundary scan paths together
  • FIG. 6 a drawing of one embodiment of PCA 200, including two independent scan paths with switches for reconfiguring the paths is shown Integrated circuits (IC's) 300 are mounted upon a printed circuit board (PCB) 250 Each IC 300 is configured for boundary scan testing In the embodiment shown, two independent scan paths are present, as represented by signal lines 400A and 400B respectively (this configuration will be illustrated m more detail with reference to Figure 7) Signal line 450 connects the two independent scan paths via switches 350S m order to form a single, common scan path Switches 350S in this embodiment mclude both multiplexers and demultiplexers When testing with the paths connected, test data is driven to PCA 200 through test point 420TDI, with test data leaving the scan chain through test point 420TDO TMS and TCK control signals are driven to test points 420TMS and 420TCK, respectively These control signals are common to both independent scan paths when they are connected to form a common scan path The individual control signals of each path are connected via switches 350T and internal signal lines
  • Figure 7 is a block diagram
  • switch control signals configure switches 350S to connect the two independent scan paths in order to form a common scan path
  • switches 350T are configured such that test control signals TMS1 and TCK1 control the entire scan cham
  • test data may be shifted m through the TDI-1 signal path of the first scan chain
  • Each IC 300 includes a plurality of boundary scan cells 330, through which the test data is shifted
  • automated test equipment such as that described m reference to Figure 5
  • Test data may be shifted out of the scan path through the TDO-2 signal path
  • Test results may be determined based on the state of each boundary scan cell during the shifting of test data
  • FIG. 8 is a block diagram illustrating an embodiment using switches to configure two parallel shared scan paths into a single scan path
  • the embodiment shown mcludes a plurality of IC's 300 configured for boundary scan testing, each including a plurality of boundary scan cells 300, which are monitored through signal pms 320 during testing
  • the two separate scan paths share a common TDI input and TDO output Switches 350S enable the two boundary scan paths to be electrically coupled, thus forming a smgle, common boundary scan path
  • the separate TMS and TCK signals I e TMS1 and TMS2, TCK1 and TCK2
  • test data may be shifted into the boundary scan path through common TDI signal path
  • test data may then be shifted through the first path (upper path m the drawing) and then through the second path before exiting the chain through the common TDO signal path
  • any number of scan paths may be combined to form a common scan path using switches to connect the paths
  • the boundary scan paths which are combined may be of different configurations
  • embodiments are contemplated wherein several independent scan paths may be combined with parallel shared scan paths to form a common boundary scan path
  • other scan path configurations not explicitly discussed here may also be combined to form a smgle scan path

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

Carte imprimée équipée (PCA), munie des chemins de balayage périphérique configurables. Une carte imprimée équipée, munie de plusieurs circuits intégrés destinés à des tests à la périphérie, comprend plusieurs commutateurs. Ces commutateurs permettent de combiner plusieurs chemins de balayage périphérique en un chemin de balayage périphérique commun. Ils peuvent également être utilisés pour combiner des chemins de balayage de différentes configurations, tels que des chemins de balayage indépendants multiples et des chemins de balayage partagés parallèles. Le type de commutateurs utilisé peut inclure des multiplexeurs, des démultiplexeurs, des relais ou autres. La PCA peut être testée sur un matériel de tests automatisés (ATE), tel qu'un contrôleur dans le circuit à lit à clous, qui est configuré pour effectuer des tests de balayage périphérique.
EP01904832A 2000-01-21 2001-01-12 Carte imprimee equipee, munie de chemins de balayage peripherique configurables Withdrawn EP1248953A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US48906000A 2000-01-21 2000-01-21
US489060 2000-01-21
PCT/US2001/000923 WO2001053845A1 (fr) 2000-01-21 2001-01-12 Carte imprimee equipee, munie de chemins de balayage peripherique configurables

Publications (1)

Publication Number Publication Date
EP1248953A1 true EP1248953A1 (fr) 2002-10-16

Family

ID=23942238

Family Applications (1)

Application Number Title Priority Date Filing Date
EP01904832A Withdrawn EP1248953A1 (fr) 2000-01-21 2001-01-12 Carte imprimee equipee, munie de chemins de balayage peripherique configurables

Country Status (5)

Country Link
EP (1) EP1248953A1 (fr)
JP (1) JP2003520967A (fr)
KR (1) KR20020087931A (fr)
AU (1) AU2001232778A1 (fr)
WO (1) WO2001053845A1 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7137053B2 (en) * 2001-09-04 2006-11-14 Verigg Ipco Bandwidth matching for scan architectures in an integrated circuit
EP1326082A1 (fr) * 2001-12-27 2003-07-09 Infineon Technologies AG Circuit integré avec trajet d'analyse
KR101222737B1 (ko) * 2010-09-27 2013-01-15 삼성전기주식회사 내장형 기판의 경계 스캔 테스트 장치 및 그 방법
KR102584095B1 (ko) 2017-12-22 2023-10-04 엘브이엠에이취 러쉐르쉐 수중유형 유화 화장품

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4340899A1 (de) * 1993-12-01 1995-06-08 Philips Patentverwaltung Meßvorrichtung zum Testen der Verbindungen zwischen wenigstens zwei Baugruppen

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO0153845A1 *

Also Published As

Publication number Publication date
KR20020087931A (ko) 2002-11-23
JP2003520967A (ja) 2003-07-08
AU2001232778A1 (en) 2001-07-31
WO2001053845A1 (fr) 2001-07-26

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