EP1518267A2 - Composant electronique encapsule dans un boitier - Google Patents

Composant electronique encapsule dans un boitier

Info

Publication number
EP1518267A2
EP1518267A2 EP03761433A EP03761433A EP1518267A2 EP 1518267 A2 EP1518267 A2 EP 1518267A2 EP 03761433 A EP03761433 A EP 03761433A EP 03761433 A EP03761433 A EP 03761433A EP 1518267 A2 EP1518267 A2 EP 1518267A2
Authority
EP
European Patent Office
Prior art keywords
contacts
layer
plastic
electronic component
layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP03761433A
Other languages
German (de)
English (en)
Inventor
Rainer Steiner
Horst Theuss
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1518267A2 publication Critical patent/EP1518267A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/012—Manufacture or treatment of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/014—Manufacture or treatment using batch processing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/121—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/10—Containers or parts thereof
    • H10W76/12—Containers or parts thereof characterised by their shape
    • H10W76/15—Containers comprising an insulating or insulated base
    • H10W76/153—Containers comprising an insulating or insulated base having interconnections in passages through the insulating or insulated base
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC]
    • H05K1/185—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC] associated with components encapsulated in the insulating substrate of the PCBs; associated with components incorporated in internal layers of multilayer circuit boards
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/681—Shapes or dispositions thereof comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/853—On the same surface
    • H10W72/856—Bump connectors and die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

  • the invention relates to an electronic component with a housing package made of several plastic layers with at least one buried conductor track and with at least one semiconductor chip and a method for the simultaneous production of several such electronic components according to the type of the independent claims.
  • connection technology in a housing package is solved by ball-shaped external contacts applied to the semiconductor chip without any wire bonding, because the external contacts can be soldered directly onto a rewiring plate or onto a circuit carrier, but there is a considerable gap between them the semiconductor chip and either the rewiring plate or a circuit carrier that has to be subsequently filled up with so-called underfill, so that although space is saved compared to the wire connection technologies, a relatively complex connection Technology between the external contacts of the semiconductor chip and a U wiring board or a circuit carrier is required.
  • the object of the invention is to provide an electronic component which can be produced inexpensively and enables an improved packaging density of semiconductor chips in a housing package.
  • an electronic component is specified with a package made of several plastic layers, which has at least one buried conductor track layer and is provided with at least one semiconductor chip.
  • This semiconductor chip has, on its outside, distributed, tapered external contacts. These tapered external contacts penetrate one of the plastic layers in the housing pack and form through contacts to the at least one buried conductor track layer.
  • pointed cone is understood to mean a body which has a base area and a height, its outer contour tapering from the base area with increasing height.
  • Such a component according to the invention can be implemented inexpensively by laminating semiconductor chips into a plastic layer without having to make expensive through contacts in the plastic layer beforehand. This enables very flat heights to be achieved, since the contacting is too the buried conductor track position practically does not contribute to the component height because external contacts disappear as intended in the plastic layer. In addition, there is no need to provide a so-called "underfill" layer for the subsequent filling of gaps between the semiconductor chip and an external conductor track layer.
  • underfill for the subsequent filling of gaps between the semiconductor chip and an external conductor track layer.
  • the housing pack has a correspondingly structured plastic layer.
  • the electronic component can be a multichip module with a plurality of buried conductor track layers and a plurality of semiconductor chips which have tapered external contacts.
  • the tapered external contacts of the semiconductor chips in the housing package of the multichip module can penetrate different plastic layers and form through contacts to different buried interconnect layers.
  • This possible embodiment of the invention shows the high flexibility of this new technology, which makes it possible to display housing packs and electronic components with such housing packs in which semiconductor chips are embedded in the housing pack and / or the housing pack is additionally equipped with semiconductor chips.
  • the invention thus makes it possible for the electronic component to have buried semiconductor chips.
  • a buried semiconductor chip in a housing package of this type consisting of a plurality of plastic layers can be realized solely by arranging a further plastic layer via a semiconductor chip, the tapered external contacts of which penetrate a plastic layer and contact a buried conductor track layer.
  • the advantage of saving space can be increased by using thinned semiconductor chips with frustoconical external contacts as semiconductor chips.
  • Such thinned semiconductor chips can have a thickness between 30 and 100 micrometers than buried semiconductor chips and are protected from damage by a covering outer plastic layer.
  • a multichip module can additionally have external contact surfaces on its upper side and / or lower side, which can be electrically connected to a higher-level circuit board or to which external contacts are applied in the form of solder balls or solder bumps.
  • a multi-chip has semiconductor chips on its top, which, with their tapered external contacts, penetrate the uppermost plastic layer and form through-contact to an underlying buried conductor layer.
  • previously prepared through contacts through a plastic layer to the buried conductor track layer can be dispensed with, since the tapered external contacts form through contacts when the uppermost plastic layer penetrates.
  • the multichip module can additionally have passive components on its upper side, which are then connected to one of the buried interconnect layers via separate through contacts in the uppermost plastic layer or to the external contact areas on the underside of the multichip module via through contacts through several plastic layers are.
  • the housing package according to the invention is to create electronic components with a hollow housing package, this hollow housing package having both the plastic layers, the buried conductor track layer and the at least one semiconductor chip with pointed conical contacts.
  • the plastic layer which directly adjoins the semiconductor chip and through which the tapered external contacts protrude, forms a frame of the hollow housing and has a recess within the frame.
  • this plastic layer through which the tapered external contacts of the semiconductor chip penetrate, is a structured plastic layer.
  • Another plastic layer can form a cover for the depressions and in this case have through contacts which are electrically connected to the tapered external contacts of the semiconductor chip.
  • the hollow housing pack consists only of two plastic layers.
  • one forms the hollow housing frame with penetrated pointed-conical external contacts of the semiconductor chip, and a further plastic layer serves to cover the hollow housing or the recess. is surrounded by the frame.
  • the semiconductor chip forms a second cover of the hollow housing package, so that there is advantageously direct access to an upper side of the semiconductor chip, with which touch sensors can be implemented.
  • the hollow housing pack can also be used to implement pressure sensors.
  • the covering plastic layer can have a central opening through which a connection to the ambient pressure and to the pressure exchange with the semiconducting one
  • the hollow housing package according to the invention can also serve as a light sensor housing or chip camera housing if the covering plastic layer is made of transparent plastic, such as acrylic glass, so that exposure of the semiconductor chip is possible.
  • the hollow housing pack can also serve as a gas sensor housing, the covering plastic layer having a central opening for gas exchange.
  • the hollow housing pack can be designed as a sound sensor, the cover having a central opening for sound recording or sound emission.
  • At least one plastic layer made of a pre-crosslinked plastic is provided, which only subsequently becomes a crosslinked and thus hardened plastic layer by thermal treatment.
  • a pre-crosslinked plastic layer can have glass fibers or carbon fiber reinforcements in order to ensure the dimensional stability of the plastic layer, although the actual crosslinking and curing has not yet taken place.
  • the invention relates not only to individual components but also to benefits which have a plurality of component positions, the benefit having a plurality of plastic layers and at least one buried conductor track layer and each component position having at least one semiconductor chip with pointed conical external contacts distributed on an outside.
  • the tapered external contacts in the panel penetrate one of the plastic layers and form through contacts to the buried conductor track layer.
  • Each component position can have a multichip module with a plurality of buried conductor track layers and with a plurality of semiconductor chips which have tapered external contacts.
  • the tapered external contacts of the semiconductor chips can penetrate different plastic layers and serve as through contacts to different buried interconnect layers.
  • the benefit can also have buried semiconductor chips, which can be thinned semiconductor chips with a thickness between 30 and 100 micrometers.
  • the benefits can be displayed extremely flat and can be delivered as a thin plate.
  • additional semiconductor chips can be arranged in each component position, which, with their tapered external contacts, are the uppermost plastic layer of the Penetrate utility and form through contact to a buried conductor track layer or are connected to through contacts which penetrate through the other plastic layers to external contact areas on the underside of the utility.
  • the benefit can also already carry all passive components of a multichip module in each of the component positions, so that the benefit does not have to be assembled by the customer first.
  • Passive components of this type can be connected to one of the buried conductor tracks via corresponding through contacts provided in the plastic layers or also to through contacts which pass through all the plastic layers and are connected to the external contact surfaces on the underside of the panel.
  • Such a use can also have a hollow housing pack in each of the component positions, which on the one hand has a plastic layer that has a recess for a hollow housing pack in each component position and is structured in such a way that it forms the frame of the hollow housing pack in each component position.
  • the hollow housing package In each component position, has at least one buried conductor track layer and at least one semiconductor chip which penetrates the frame-forming plastic layer with its tapered external contacts and forms through contact with the buried conductor track layer.
  • a further plastic layer can be provided with through contacts as a cover to complete the hollow housing pack.
  • the plastic layers which are provided for penetration of tapered external contacts of a semiconductor chip, can have pre-crosslinkable plastic layers, which has the advantage that the pre-crosslinkable plastic layers only after penetration of the tapered external contacts of the semiconductor chip.
  • chip can be cross-linked in a thermal process to hardened plastic layers or thermosets.
  • the pre-crosslinkable plastic layers so-called “pre-packs”, can have glass fibers or carbon fiber reinforcements in order to ensure limited dimensional stability even in the pre-crosslinked state.
  • a method for producing at least one electronic component with a housing package made of a plurality of plastic layers with at least one buried conductor layer and at least one semiconductor chip which has pointed conical external contacts distributed on an outside has the following method steps:
  • a circuit carrier with external contact surfaces on the underside of the circuit carrier and with a conductor track layer on the top of the circuit carrier is produced, the outer contact surfaces and the conductor track layer being electrically connected through contacts through the circuit carrier.
  • semiconductor chips with pointed conical external contacts can be produced on semiconductor wafers in order to use them after the semiconductor wafer has been separated into individual semiconductor chips with pointed conical external contacts for producing an electronic component with a package.
  • a pre-cross-linked plastic layer is applied to the circuit carrier or to the conductor track layer on the top of the circuit carrier. This pre-networked
  • Plastic layer can be converted into a viscous state, so that the semiconductor chips can advantageously be placed on the pre-crosslinked plastic with minimal pressure load. can be applied.
  • the tapered external contacts of at least one semiconductor chip penetrate the pre-crosslinked plastic layer until they form through contacts to the conductor track layer on the top of the circuit carrier and the semiconductor chip impresses itself in the pre-crosslinked plastic layer.
  • the pre-cross-linked plastic layer is hardened and cross-linked to form a plastic layer.
  • the functional test of the electronic component can be carried out via the external contact surfaces of the circuit carrier.
  • a further pre-cross-linked plastic layer can be applied to the semiconductor chip before the pre-cross-linked plastic layer has hardened and cross-linked.
  • This plastic layer covers the semiconductor chip and protects it from mechanical damage. This results in a housing package made of several plastic layers with a buried semiconductor chip.
  • the contact surfaces of semiconductor chips are provided with acicular external contacts. These tapered external contacts are pressed through a plastic layer for contacting. On the side of the plastic layer opposite the semiconductor chip, the tapered external contacts meet a metallization of a circuit carrier with which an electrical contact is formed.
  • This technology can also be used to implement electronic components which, in addition to buried conductor track layers, also have buried semiconductor chips, in that at least one further plastic layer is arranged above the semiconductor chips.
  • Housing packs can be realized analogously to flip-chip packs, without the need for so-called "underfill layers”.
  • Ultra-thin semiconductor chips which in turn have improved flexibility, allow these semiconductor chips to be embedded between substrate layers, which minimizes the overall height by the fact that the external contacts do not impair the component height, because the conical external contacts can disappear in the plastic layer of the substrate.
  • Complex multichip modules can be realized with the technology according to the invention, which can have contacts on both sides, namely on the top and / or the bottom, and which have additional semiconductors.
  • terchips and / or passive components can be equipped on their top or / and bottom.
  • the contacts created by pressing the tapered contacts into a plastic layer are so reliable that they can be used in high-performance burial applications, such as in high-frequency technology.
  • this panel can be implemented in the standard PCB format 18 "x 24".
  • the PCB panel can be separated into several assembly panels and one of them
  • the final electronic component can be generated with a housing package by surface-mounting by subsequent singulation using sawing or breaking.
  • an additional heat treatment can possibly be carried out simultaneously under pressure on the entire housing packaging when the pre-crosslinked plastic layers harden.
  • FIG. 1 shows a schematic cross section of an electronic component of a first embodiment of the invention
  • FIG. 2 shows a schematic cross section of an electronic component of a second embodiment of the invention
  • FIG. 3 shows a schematic cross section of an electronic component of a third embodiment of the invention
  • FIG. 4 shows a schematic cross section of an electronic component of a fourth embodiment of the invention
  • FIG. 5 shows a schematic cross section of an electronic component of a fifth embodiment of the invention
  • 6 to 12 show schematic cross sections through components of a panel according to method steps for producing an electronic component according to the first
  • FIG. 6 shows a schematic cross section through a circuit carrier of a panel with a conductor track layer on its upper side, with external contact areas on its underside and with through contacts to the external contact areas in a component position of the panel.
  • FIG. 7 shows a schematic cross section through a circuit carrier of a panel after a pre-crosslinked plastic layer has been applied to the top of the circuit carrier
  • FIG. 8 shows a schematic cross section through a semiconductor chip with tapered external contacts after alignment in a component position of the panel
  • Figure 9 shows a schematic cross section through a
  • FIG. 10 shows a schematic cross section through a further pre-crosslinked uppermost plastic layer
  • FIG. 11 shows a schematic cross section through a panel after application of the further, pre-crosslinked, uppermost plastic layer and curing of the plastic layers of the panel with electrical connection of the tapered external contacts of the semiconductor chip to the buried conductor track layer,
  • FIG. 12 shows a schematic cross section through an electronic component after the utility has been separated into individual electronic components.
  • Figure 1 shows a schematic cross section of an electronic component 1 of a first embodiment of the invention.
  • the reference numeral 2 denotes a housing pack, which is composed of three plastic layers 3. Between at least one buried conductor track layer 4 is arranged in the plastic layers 3. This conductor track layer 4 lies on the upper side 27 of a circuit carrier 26 which carries the housing package.
  • the circuit carrier 26 of this embodiment of the invention has a plastic layer 3, on the top 27 of which the buried conductor track layer is arranged and which is electrically connected via through contacts 8 to external contact surfaces 14 arranged on the underside 28 of the circuit carrier 26.
  • external contact balls 29 of the electronic component 1 are arranged on the external contact surfaces 17.
  • the reference numeral 22 denotes a pre-crosslinkable
  • the housing package 2 is closed by an uppermost plastic layer 15, which likewise consists of a pre-crosslinked plastic 22 and covers a rear side 30 of the semiconductor chip 5, so that the semiconductor chip 5 is a buried semiconductor chip 10.
  • the housing package 2 made of the three plastic layers 3 with the one buried conductor track structure 4 can not only be manufactured extremely inexpensively but also very compactly and thus with an extremely low overall height, in particular when the semiconductor chip 5 is a thinned semiconductor chip 11, which has a thickness between 30 to 100 micrometers and in extreme cases can assume a thickness below 30 micrometers.
  • the total component height, which essentially results from the layer thicknesses of the three plastic layers, can be between 100 and 500 micrometers between the bottom 12 and the top 13.
  • FIG. 2 shows a schematic cross section of an electronic component 1 of a second embodiment of the invention.
  • Components with the same functions as in FIG. 1 are identified by the same reference symbols and are not discussed separately.
  • the second embodiment of the invention represents a multi-chip module in schematic cross section, which in this embodiment and in this cross section has three semiconductor chips 31, 32 and 33 which are arranged in different positions in or on the housing package 2 of the multi-chip module 9.
  • two buried conductor track layers 34 and 35 are arranged between three plastic layers 3.
  • the circuit carrier 26 is also made of a pre-cross-linkable plastic 22, so that the semiconductor chip 31 with its passive rear side 30 can be stamped into the pre-cross-linked plastic 22 before the plastic layers 3 are completely cross-linked.
  • the active upper side of the semiconductor chip 31 has tapered external contacts 7, which penetrate through the central plastic layer 3 of the multichip module as through contacts 8 and are connected to the interconnect layer 35 between the uppermost two plastic layers.
  • the semiconductor chip 32 as a buried semiconductor chip 10 is analogous to the first embodiment According to the invention, the lower conductor track layer 35 of the buried conductor track layers 4 is arranged and contacted, with its tapered external contacts likewise penetrating the middle plastic layer of the housing pack 2.
  • the third semiconductor chip 33 is on this multichip module 9
  • Top 13 arranged and penetrates with its tapered external contacts 7, the top plastic layer 15 of the multichip module.
  • the multichip module can be equipped with further semiconductor chips 5 as well as with passive components 16 on its upper side 13, while its underside 12 has external contact surfaces 14 which can be equipped with external contact balls (not shown).
  • the passive components 16 can be connected both with their electrodes via contacts to the individual buried interconnect layers 34 or 35 and also directly with the external contact areas 8.
  • Such an electronic component 1 according to the invention is distinguished by the fact that no bond connections are to be provided and the through contacts to be prepared in the individual plastic layers 3 can also be minimized, especially since the pointed-conical external contacts 7 of the semiconductor chips form through contacts 8 through the individual plastic layers 3.
  • FIGS 3 to 5 show special forms of electronic
  • FIG. 3 shows a schematic cross section of an electronic component 1 of a third embodiment of the invention, with which a first hollow housing pack 17 is realized which has an extremely flat cavity 36.
  • the housing package 2 of this cavity housing package 17 essentially has two plastic layers.
  • a structured plastic layer 37 which forms the frame 19 for the cavity housing package, the frame 19 being penetrated by pointed-conical external contacts 7 of the semiconductor chip 5.
  • Semiconductor chip 5 simultaneously forms the upper side 13 of the electronic component 1 with one of its surfaces.
  • the recess 25 in the structured plastic layer 37 is covered by a closed plastic layer in the form of a cover 18, which has similar functions to the circuit carrier 26 in the previous exemplary embodiments, because the cover 18 simultaneously carries a buried conductor layer 4, which has through contacts 8 Outer contact surfaces 14 on the cover 18 are connected.
  • a cavity housing package 17, as shown in FIG. 3 can be used for contact sensors such as are provided in notebooks, computers or ATMs, especially since an upper side of the semiconductor chip 5 simultaneously forms the upper side 13 of the sensor, while the shielding 18 of the cavity 36 has the underside 12 of this cavity housing package.
  • FIG. 4 shows a schematic cross section of an electronic component 1 of a fourth embodiment of the invention.
  • This fourth embodiment of the invention differs from the third embodiment of the invention according to FIG. 3 in that the semiconductor chip 5 is buried
  • Semiconductor chip 10 is formed by an upper plastic layer 15 covering the semiconductor chip 5 and at the same time protecting against contact.
  • Such an electronic component with a flat cavity 36 can be used in particular for precise high-frequency filters, the filter structure being arranged on the active top side 6 of the semiconductor chip 5 and via the tapered external contacts 7 of the semiconductor chip 5 with through contacts 8 through the cover 18 of the cavity housing package 17 is connected to external contact surfaces 14 on the underside 12 of the housing pack 2.
  • the housing package consists of three plastic layers 3 with a buried conductor track layer 4, while the housing package 2 in the third embodiment of the invention has only two plastic layers 3 with a buried conductor track layer 4 in between.
  • FIG. 5 shows a schematic cross section of an electronic component 1 of a fifth embodiment of the invention.
  • This fifth embodiment of the invention differs from the fourth embodiment in that the cover 18 has a central opening 21 to the cavity 36.
  • This central opening is used for gas coupling, for example of a gas sensor, or can also be used for sound coupling of a sound sensor, such as a microphone or a microphone.
  • FIGS. 6 to 12 show schematic cross sections through components of a panel 24 after individual method steps for producing an electronic component 1 according to the first embodiment of the invention.
  • Components of Figures 6 to 12, the same functions as in the previous fi guren meet, are identified with the same reference numerals.
  • Figure 6 shows a schematic cross section through a circuit board 26 of a panel 24 with a conductor layer 4 on its top 27, with external contact surfaces 14 on its underside 28 and with through contacts 8 to the external contacts 14 in a component position 23.
  • a circuit board 26 can be used to reinforce the Dimensional stability can be reinforced with glass fibers or carbon fibers.
  • the dotted lines 38 indicate the limits of a component position 23 of the panel 24.
  • the circuit carrier can already consist of cross-linked plastic and have a structured copper layer as the conductor track layer 4 on its upper side. This interconnect layer 4 is connected via contacts 8 made of copper or a copper alloy to external contact surfaces 14, which are provided on the underside 28 of the circuit board 26.
  • FIG. 7 shows a schematic cross section through a circuit carrier 26 of a panel 24 after a pre-cross-linked plastic layer 22 has been applied to the top 27 of the circuit carrier 26.
  • a pre-cross-linked plastic layer 22 is relatively soft in relation to the already cross-linked and hardened plastic of the circuit carrier 26 and can therefore be deformed without great effort.
  • This deformability of a pre-crosslinked plastic is used in the next step, which is shown with FIGS. 8 and 9, in order to reduce the manufacturing costs of electronic components.
  • FIG. 8 shows a schematic cross section through a semiconductor chip 5 or a thinned semiconductor chip 11 tapered external contacts 7 after alignment of the semiconductor chip 5, 11 over a component position 23 of the panel 24.
  • This semiconductor chip 5, 11 is pre-cross-linked with its tapered external contacts 7 over the plastic layer 3!
  • Plastic 22 is arranged and after the positioning, which is shown in Figure 8, in Figure 9 penetrate the plastic layer 3 with its tapered external contacts.
  • FIG. 9 shows a schematic cross section through a component position 23 of a panel 24 after penetration of the pre-crosslinked plastic layer 22 with the pointed-conical external contacts of the semiconductor chip 5, 11 and after contacting the pointed-conical external contacts 7 of the semiconductor chip 5, 11 with a buried conductor track layer 4.
  • the interconnect layer originally arranged on the upper side 27 of the circuit carrier 26 becomes a buried interconnect layer 4.
  • this buried interconnect layer 4 after penetrating the plastic layer 3 with the aid of the tapered external contacts 7 of the semiconductor chip 5 with the semiconductor chip 5 contacted.
  • the outside 6 of the semiconductor chip 5, which carries the pointed-conical external contacts 7, is stamped into the pre-crosslinked plastic layer 22.
  • FIG. 10 shows a schematic cross section through a further pre-crosslinked uppermost plastic layer 15 of a panel 24 after positioning over a component position 23 with a semiconductor chip 5.
  • FIG. 11 shows a schematic cross section through a panel 24 after application of the further pre-crosslinked uppermost plastic layer 15 and hardening of the plastic layers 15 and 22 of the panel 24 with electrical connection of the tapered external contacts 7 of the semiconductor chip 5 to the buried conductor layer 4.
  • FIG. 11 thus shows the result of two process steps, namely the application of the positioned topmost plastic layer 15 in the direction of arrow A, as shown in FIG.
  • a plurality of electronic components are simultaneously produced in the component positions 23 of the benefit.
  • the use can be carried out in a standard PCB format of 18 "x 24".
  • the panel can be separated into several assembly panels and after surface mounting of additional components, singulation can be performed by sawing, milling or by breaking the panel to individual multichip modules.
  • FIG. 12 shows a schematic cross section through an electronic component 1 after the panel 24 has been separated into individual electronic components 1.
  • the schematic cross section as shown in FIG. 12 thus corresponds to the schematic cross section as is already known from FIG.
  • the external contact balls 29, which are shown here only after the electronic components 1 have been separated, can also be applied to the external contact surfaces 14 of the panel during manufacture of the panel before the panel is separated into individual electronic components 1 by sawing, milling or breaking.

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Packaging Frangible Articles (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

L'invention concerne un composant électronique encapsulé dans un boîtier (2) constitué de plusieurs couches de matière plastique (3), ledit composant comprenant au moins une couche de tracés conducteurs (4) enterrés et au moins une puce à semi-conducteurs (5) qui présente des contacts extérieurs (7) en forme d'ogives, répartis sur son côté extérieur (6). Les contacts extérieurs (7) en forme d'ogives pénètrent dans une des couches de matière plastique (3) et forment des contacts traversants en direction de la couche de tracés conducteurs (4) enterrés. L'invention concerne en outre un procédé pour produire un tel composant électronique (1).
EP03761433A 2002-06-26 2003-06-25 Composant electronique encapsule dans un boitier Withdrawn EP1518267A2 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10228593 2002-06-26
DE10228593A DE10228593A1 (de) 2002-06-26 2002-06-26 Elektronisches Bauteil mit einer Gehäusepackung
PCT/DE2003/002119 WO2004003991A2 (fr) 2002-06-26 2003-06-25 Composant electronique encapsule dans un boitier

Publications (1)

Publication Number Publication Date
EP1518267A2 true EP1518267A2 (fr) 2005-03-30

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EP03761433A Withdrawn EP1518267A2 (fr) 2002-06-26 2003-06-25 Composant electronique encapsule dans un boitier

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US (1) US7319598B2 (fr)
EP (1) EP1518267A2 (fr)
DE (1) DE10228593A1 (fr)
WO (1) WO2004003991A2 (fr)

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Also Published As

Publication number Publication date
DE10228593A1 (de) 2004-01-15
WO2004003991A3 (fr) 2004-04-01
WO2004003991A2 (fr) 2004-01-08
US7319598B2 (en) 2008-01-15
US20060126313A1 (en) 2006-06-15

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