EP1525619A1 - Composant a semiconducteur pour montage en surface et procede de fabrication - Google Patents

Composant a semiconducteur pour montage en surface et procede de fabrication

Info

Publication number
EP1525619A1
EP1525619A1 EP03787632A EP03787632A EP1525619A1 EP 1525619 A1 EP1525619 A1 EP 1525619A1 EP 03787632 A EP03787632 A EP 03787632A EP 03787632 A EP03787632 A EP 03787632A EP 1525619 A1 EP1525619 A1 EP 1525619A1
Authority
EP
European Patent Office
Prior art keywords
film
semiconductor
chip
field
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP03787632A
Other languages
German (de)
English (en)
Inventor
Georg Bogner
Jörg Erich SORG
Günter Waitl
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ams Osram International GmbH
Original Assignee
Osram Opto Semiconductors GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE10234978A external-priority patent/DE10234978A1/de
Application filed by Osram Opto Semiconductors GmbH filed Critical Osram Opto Semiconductors GmbH
Publication of EP1525619A1 publication Critical patent/EP1525619A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/014—Manufacture or treatment using batch processing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/8506—Containers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/857—Interconnections, e.g. lead-frames, bond wires or solder balls
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/688—Flexible insulating substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/016—Manufacture or treatment using moulds
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

  • the invention relates to a surface-mountable semiconductor component having a semiconductor chip, at least two external electrical connections which are electrically conductively connected to at least two electrical contacts of the semiconductor chip, and a chip cladding. It further relates to a method for producing such a semiconductor component.
  • Luminescent diode housings are now available with a footprint of size 0402 (corresponding to 0.5 mm x 1.0 mm) and a component height of 400 ⁇ m - 600 ⁇ m. See data sheet from FAIRCHILD SEMICONDUCTOR® for type QTLP690C-X. The corresponding component concept is described in US Pat. No. 4,843,280.
  • the present invention is based on the object of providing a concept for a surface-mountable semiconductor component, in particular a surface-mountable miniature luminescent diode and / or photodiode, which allows the size to be reduced further.
  • This object is achieved by a surface-mountable semiconductor component with the features of claim 1 and by a method with the features of claim 18.
  • the two external electrical connections are formed on a film, the thickness of which is less than or equal to 100 ⁇ m, in particular less than or equal to 50 ⁇ m.
  • This film is preferably made of plastic material, in particular PI or PEN.
  • the semiconductor chip is on a first one
  • Main surface of the film attached and the chip wrap is applied essentially exclusively on the first main surface.
  • the invention is based in particular on the idea of
  • the design according to the invention is preferably suitable for use in the case of components emitting and / or receiving electromagnetic radiation with one or more semiconductor chips emitting and / or receiving electromagnetic radiation, in particular for luminescent diode components with a housing footprint of the size 0402 (corresponding to 0.5 mm x 1.0 mm) or smaller and a component height of less than 400 ⁇ m, in particular less than 350 ⁇ m.
  • the chip envelope made of an electromagnetic radiation is permeable, in particular whose transparent or translucent material is manufactured, in particular from an electromagnetic radiation transparent, preferably unfilled clear plastic material.
  • the chip casing can be mixed with a phosphor which absorbs at least part of the electromagnetic radiation emitted by the luminescence diode chip and emits electromagnetic radiation of a different wavelength and color than the absorbed radiation.
  • the chip casing is preferably produced by means of an injection molding process.
  • the film including the external electrical connections, is preferably coated with a cover layer which provides adhesion to the chip encapsulation and which has mounting windows at the chip mounting points and at the wire mounting points in which there is no cover layer.
  • two external electrical connections are each from a first electrical connection area on the first Main surface of the film, a second electrical connection area on the second main surface of the film and at least one electrical lead-through through the film, which electrically connects the first connection area to the associated second connection area.
  • the electrical connection areas are preferably produced by means of structured metal layers on the film. Conventional suitable methods can be used to structure the metal layers.
  • the metal layers are constructed in multiple layers and, viewed from the film, preferably have a first layer made of copper or a copper-based alloy, which is responsible for the electrical conduction of the metal layer, and a second layer made of nickel or a nickel-based alloy, which represents a barrier layer , and a third layer of gold or a gold-based alloy, which serves to improve the bondability and solderability of the metal layer.
  • the metal layers on the chip side, as seen from the plastic film preferably have a copper layer, followed by a nickel layer, on which in turn a NiP layer (phosphorus content, for example, between 5% and 15%, preferably 8%) is applied.
  • the NiP layer advantageously has a higher reflectivity than a Ni layer and is at least as well bondable as a Ni layer. In addition, it advantageously has a significantly lower tendency to tarnish (oxidize) than a Ni layer.
  • the metal layers located on the back of the lead frame then point out, in particular to simplify the manufacture of the lead frame, as seen from the plastic layer preferably the same layer sequence.
  • a gold layer can preferably be applied to the NiP layer.
  • the first layer expediently has a thickness of between 5 ⁇ m and 25 ⁇ m inclusive.
  • the latter is fastened to one of the first two electrical connection areas by means of a thermally highly conductive connecting means and the corresponding external electrical connection is designed such that it represents a sufficiently good thermal connection for the semiconductor chip.
  • a thermally highly conductive connecting means and the corresponding external electrical connection is designed such that it represents a sufficiently good thermal connection for the semiconductor chip.
  • the semiconductor chip can be mounted on the associated electrical connection area both with its substrate side (i.e. upside-up assembly) and with its epitaxial layer side (i.e. upside-down or flip-chip assembly).
  • the connecting means is, for example, a sufficiently thermally conductive adhesive or a metallic solder.
  • the chip cladding is preferably in a central area above the semiconductor chip and, if necessary. one or more bonding wires to the semiconductor chip, perpendicular to the film, to a greater thickness than in an edge area surrounding the central area.
  • the volume of the chip wrapper is advantageously reduced, as a result of which curvature of the film during the production process can be counteracted due to different thermal expansions of the film and chip wrapper.
  • the opposite ends of the external electrical connections have mutually projecting areas in which the electrical feedthroughs are arranged through the film are.
  • the opposite ends of the external electrical connections preferably run in an S-like manner such that the projecting parts overlap.
  • a film strip is first produced which has on both sides structured and through-contacted through the film strip electrically conductive layers that there is at least one field from a plurality of arranged side by side, component areas having external electrical connections.
  • Each of the component areas comprises all structures of the electrically conductive layers for all external electrical connections of the later semiconductor component.
  • At least one semiconductor chip is subsequently applied to each of the component regions and electrically connected to the external electrical connections.
  • the field is then placed in an injection mold in which a single cavity is provided for the entire field and spans all the semiconductor chips in the field and there essentially only forms cavities on the side of the semiconductor chips.
  • the injection of wrapping material into the cavity is preferably carried out from the side and in particular via film sprue.
  • the field is removed from the injection mold and separated into individual semiconductor components by cutting the chip encapsulation material and the film strip with the structured electrically conductive layers between the component regions.
  • the cavity has a large number of recesses, each of which spans one or more semiconductor chips. In this way, the volume of encapsulation material is reduced by reducing the thickness of the encapsulation material in areas where this is permissible compared to the thickness in the area of semiconductor chips and possibly one or more bonding wires to the semiconductor chip.
  • a separate recess is preferably provided above each semiconductor chip of the field, such that the wrapping material has a multiplicity of elevations arranged next to one another after the injection molding process, in particular has a structure similar to a chocolate bar.
  • the field is advantageously separated by cutting through the wrapping material and the film strip with the structured electrically conductive layers in the trenches between the elevations.
  • an adhesion promoter is applied to the film and / or the electrically conductive layers, which improves the adhesion of the wrapping material to the film and / or the electrically conductive layers.
  • a PI topcoat is preferably used for this.
  • the adhesion promoter is preferably applied in each case to the entire component area, except for the chip mounting areas on which the semiconductor chips are attached and, if appropriate, on the wire mounting areas on which connecting wires are attached.
  • the bonding agent has contacting windows in these areas.
  • the film strip with the structured electrically conductive layers is laminated with its back onto an auxiliary film before being inserted into the injection mold.
  • this auxiliary film protects the electrical connections from mechanical damage (e.g. scratching) and, on the other hand, against undesired covering of the connections with wrapping material, i.e. against a so-called flash on the back of the film strip.
  • the auxiliary film expediently has a similar or a greater coefficient of thermal expansion than the wrapping material, in such a way that it counteracts as far as possible warping of the field due to a greater shrinkage of the wrapping material compared to the film strip during its hardening and / or cooling after the extrusion coating of the field.
  • the film strip can have bores, openings and / or slots outside the fields to reduce mechanical stresses due to different thermal expansions and / or material shrinkages.
  • the film strip can be made of a material which has a thermal expansion coefficient similar to that of the wrapping material.
  • a cambered injection mold can be used, in which the field is seen from the side during which the encapsulant is injected into the cavity, on which later the material with the larger outer thermal expansion coefficient is located, is convexly curved.
  • the field is applied to a film with the wrapping side before being separated, and the auxiliary film is subsequently removed from the back of the film, if necessary.
  • this film is preferably transparent to electromagnetic radiation and the measurement is carried out through the film.
  • the field is preferably separated by sawing, laser cutting and / or water jet cutting.
  • Wafermap are delivered.
  • the components can be separated, taped and delivered after the chip test as before.
  • Figure 1 is a schematic sectional view through the semiconductor device according to the embodiment
  • Figure 2 is a schematic representation of a plan view of the front of a section of a film strip
  • Figure 3 is a schematic representation of a top view of the back of the detail of Figure 2;
  • Figure 4 is a partial schematic representation of a sectional view of an injection mold with inserted film strip
  • FIG. 5 shows a partial schematic representation of a sectional view of a film strip with coated semiconductor chips
  • Figure 6 is a partial schematic representation of a plan view of a film strip with enveloped
  • FIG. 7 shows an enlarged schematic illustration of a section of the film strip shown in FIG. 6.
  • the semiconductor component according to the invention shown in FIG. 1 is a surface-mountable miniature light-emitting diode component with a footprint of type 0402.
  • two external electrical connections 3, 4 are formed on a plastic film 2, which are made, for example, of polyimide (PI) or Pelyethylene naphthalate (PEN).
  • the thickness of the Plastic film is approximately 50 ⁇ m or less.
  • a light-emitting diode chip 1 is attached to a first main surface 22 of the plastic film 2 and there is encapsulated with a chip cladding 5 which is applied to the first main surface 22.
  • the chip casing 5 preferably consists of a clear plastic material, preferably an unfilled clear epoxy resin material, which can be processed by means of injection molding or transfer molding.
  • the two external electrical connections 3, 4 each consist of a first metallized region 31, 32 on the first main surface 22 of the film 2, a second metallised region 41, 42 on the second main surface 23 of the film 2 and at least one metallic electrical feedthrough 314, 324 through the film 2, which electrically connects the first metallized region 31, 32 to the associated second metallized region 41, 42.
  • the metallized regions 31, 32, 41 and 42 each have a plurality of layers and, viewed from the film 2, contain in succession an electrical conductor layer comprising copper or a copper-based alloy and a barrier layer comprising nickel or a nickel-based alloy.
  • an electrical conductor layer comprising copper or a copper-based alloy
  • a barrier layer comprising nickel or a nickel-based alloy.
  • gold or gold-based alloy connection layer is provided on the barrier layer.
  • Copper-based alloy, nickel-based alloy or gold-based alloy are understood to mean all alloys whose properties are essentially determined by copper, nickel or gold.
  • the metallized areas 31 and 32 located on the chip side, viewed from the plastic film 2 preferably have a copper layer, followed by a nickel layer, on which in turn a NiP layer (phosphorus content, for example, between 5% and 15%, preferably 8% ) applied is.
  • the NiP layer advantageously has a higher reflectivity than a Ni layer and is at least as easily bondable as a Ni layer. In addition, it advantageously has a significantly lower tendency to tarnish (oxidize) than a Ni layer.
  • the metallized areas 41 and 42 located on the back preferably have the same layer sequence, as seen from the plastic layer 2.
  • a gold layer can preferably be applied to the NiP layer.
  • the thickness of the electrical conductor layer is between 5 and 25 ⁇ m inclusive.
  • the light-emitting diode chip 1 is fastened on the electrical connection area 31 by means of a thermally highly conductive connecting means and the associated external electrical connection 31, 314, 41 is designed such that it can be used as a thermal connection for the light-emitting diode chip.
  • the light-emitting diode chip can be mounted on the electrical connection region 31 both with its substrate side (i.e. upside-up assembly) and with its epitaxial layer side (i.e. upside down or flip-chip assembly).
  • the connecting means is, for example, a sufficiently thermally conductive adhesive or a metallic solder.
  • the chip cladding 5 preferably has a smaller thickness in an edge region 52 to its side edge in the direction perpendicular to the film than in a central region 51, which at least holds the semiconductor chip 1 and possibly. spanned one or more bonding wires 6 to the LED chip 1. This is indicated in FIG. 1 by the dashed lines 53, 54 and can be seen in FIGS. 5, 6 and 7.
  • the lateral dimensions of the surface-mountable light-emitting diode component are at most - 0.5 mm ⁇ 1 mm and the component height is less than or equal to 0.4 mm, preferably less than or equal to 0.35 ⁇ m.
  • the wrapping material can be mixed with a phosphor that absorbs at least part of the electromagnetic radiation emitted by the LED chip and electromagnetic radiation of a greater wavelength than the absorbed radiation is emitted.
  • the opposite ends of the external electrical connections 3, 4 each have an S-like course, in each of which a projecting part of one end projects into a recessed part of the other end.
  • the electrical feedthroughs 314, 315 are each arranged in a projecting part of the S-like ends.
  • a film strip 200 is first produced, which is provided on both sides with electrically conductive layers 203, 204 which are structured in such a way and through which the film strip is plated through by means of metallic leadthroughs that a field 201 consists of a multiplicity of adjacent ones - Component regions 202 arranged one above the other is formed.
  • the front side of the film strip 200 with the front metallization structure 203 is shown in FIG. 2, and the rear side of the film strip 200 with the rear metallization structure 204 is shown in FIG. 3.
  • a component area is indicated in the enlarged sections of FIGS. 2 and 3 by the dash-dotted lines 202.
  • Each of the component areas 202 has front and back
  • the back of the film strip 200 each have a metallization structure 203, 204, which together with electrical feedthroughs 314, 324 (see FIG. 7) form a first 3 and a second external electrical contact 4.
  • a light-emitting diode chip 1 is applied to each of the component areas, specifically directly to the structured, metallized area 31.
  • the connection between the light-emitting diode chip 1 and the metallic layer 31 takes place by means of an electrically and thermally conductive adhesive which electrically contacts the back of the light-emitting diode chip 1 as well as thermally contacted with the metallic layer 31 of the external electrical connection 3.
  • a front-side contact of each light-emitting diode chip 1 is then connected to the metallic layer 32 of the associated external electrical connection 4 by means of a bonding wire 6 in each case.
  • the field 201 provided with the light-emitting diode chips 1 and the plurality of light-emitting diode chips 1 are transformed into one
  • Injection mold 500 inserted (see FIG. 4).
  • this mold 500 at least one cavity 501 is formed, which spans all the semiconductor chips 1 of the field 201 and only leaves a cavity for the encapsulant on the side of the LED chips 1 above the film strip.
  • the wrapping material is subsequently injected into this cavity, preferably by means of a film sprue from one side of the cavity.
  • the cavity 501 has a plurality of recesses 502, which are each positioned above a semiconductor chip 1 during injection molding. Consequently, the thickness of the chip cladding 5 is made larger in the areas of the light-emitting diode chips 1 and the bonding wires 6 than in the remaining area of the field 201.
  • the wrapping material has a large number of raised areas 51 arranged next to one another, so that the field as a whole has a structure similar to that of a chocolate bar structure (see FIGS. 6 and 7).
  • the extrusion-coated light-emitting diode field 201 is removed from the injection mold 500 and is preferably applied with the back of the film strip 200 to an adhesive film 400 (cf. FIG. 5).
  • This application to an adhesive film 400 serves to hold the field 201 together during and after a later separation into individual light-emitting diode components.
  • the field 201 is separated by severing the chip encapsulation material and the film strip 200 with the structured metallizations 203, 204 between the component regions 202, that is to say in the trenches 52 between the elevations 51 of the encapsulation material 50.
  • Conventional methods such as sawing, laser cutting or water jet can be used for this - cutting can be used.
  • an adhesion promoter in particular in the form of a top coat made of polyimide, is applied to the film strip 200 and / or the electrically conductive layers 203, 204.
  • the adhesion promoter is preferably in each case applied to the entire area of the field 201, except for the chip mounting areas in which the light-emitting diode chips 1 are mounted and contacted on the assigned external electrical connections 3, and except for the wire mounting areas on which the bonding wires 6 are connected to the associated external electrical connections 4 ,
  • the film strip 200 with the structured metallization layers 203, 204 is laminated onto an auxiliary film before insertion into the injection mold 500, which film has a similar or a greater coefficient of thermal expansion than the wrapping material.
  • the auxiliary film can thus counteract warping of the field due to a greater shrinkage of the wrapping material 50 compared to the film strip 200 during its hardening and / or cooling after the field 201 is encapsulated.
  • the auxiliary film can subsequently take over the function of the adhesive film described above when separating.
  • a further measure to counteract the warping of the field due to mechanical tension due to different thermal expansions and / or material shrinkage of the wrapping material and film strips is the formation of bores, openings and / or slots 210 outside the field 201.
  • a film strip 200 can be used which consists of a material which has a similar coefficient of thermal expansion as the wrapping material 50.
  • a domed injection mold can be used for the same reason, in which the field 201 is convexly curved as seen from the side of the light-emitting diode chips 1 during the injection of the enveloping mass 50 into the cavity 501.

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Led Device Packages (AREA)
  • Injection Moulding Of Plastics Or The Like (AREA)

Abstract

L'invention concerne un composant à semiconducteur pour montage en surface comprenant une puce semiconductrice (1), au moins deux connexions électriques extérieures (3, 4), reliées de façon électroconductrice à au moins deux contacts électriques de cette puce semiconductrice (1), et une enveloppe de puce (5). Ces deux connexions électriques extérieures (3,4) sont situées sur une feuille (2) présentant une épaisseur inférieure ou égale à 100 ñm. Cette puce semiconductrice (1) est fixée à une première surface principale (22) de ladite feuille (2) et l'enveloppe de puce (5) est appliquée sur cette première surface principale (22). Ladite invention concerne également un procédé de fabrication d'un composant de ce type.
EP03787632A 2002-07-31 2003-07-07 Composant a semiconducteur pour montage en surface et procede de fabrication Withdrawn EP1525619A1 (fr)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
DE10234978A DE10234978A1 (de) 2002-07-31 2002-07-31 Oberflächenmontierbares Halbleiterbauelement und Verfahren zu dessen Herstellung
DE10234978 2002-07-31
DE10244888 2002-09-26
DE10244888 2002-09-26
PCT/DE2003/002259 WO2004017407A1 (fr) 2002-07-31 2003-07-07 Composant a semiconducteur pour montage en surface et procede de fabrication

Publications (1)

Publication Number Publication Date
EP1525619A1 true EP1525619A1 (fr) 2005-04-27

Family

ID=31889088

Family Applications (1)

Application Number Title Priority Date Filing Date
EP03787632A Withdrawn EP1525619A1 (fr) 2002-07-31 2003-07-07 Composant a semiconducteur pour montage en surface et procede de fabrication

Country Status (6)

Country Link
US (2) US7199470B2 (fr)
EP (1) EP1525619A1 (fr)
JP (1) JP2005535144A (fr)
CN (1) CN1672260A (fr)
TW (1) TWI227569B (fr)
WO (1) WO2004017407A1 (fr)

Cited By (2)

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Publication number Priority date Publication date Assignee Title
US8872330B2 (en) 2006-08-04 2014-10-28 Osram Opto Semiconductors Gmbh Thin-film semiconductor component and component assembly
US9142720B2 (en) 2007-01-29 2015-09-22 Osram Opto Semiconductors Gmbh Thin-film light emitting diode chip and method for producing a thin-film light emitting diode chip

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JP3764160B2 (ja) * 2004-09-10 2006-04-05 三井金属鉱業株式会社 キャパシタ層形成材及びキャパシタ層形成材を用いて得られる内蔵キャパシタ回路を備えるプリント配線板。
DE102005055293A1 (de) * 2005-08-05 2007-02-15 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung von Halbleiterchips und Dünnfilm-Halbleiterchip
US8044412B2 (en) 2006-01-20 2011-10-25 Taiwan Semiconductor Manufacturing Company, Ltd Package for a light emitting element
US8678271B2 (en) * 2007-06-26 2014-03-25 Globalfoundries Inc. Method for preventing void formation in a solder joint
TWI348230B (en) * 2007-08-08 2011-09-01 Huga Optotech Inc Semiconductor light-emitting device with high heat-dissipation efficiency and method of fabricating the same
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TW200406071A (en) 2004-04-16
US20050212098A1 (en) 2005-09-29
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JP2005535144A (ja) 2005-11-17
US20070184629A1 (en) 2007-08-09
CN1672260A (zh) 2005-09-21
US7199470B2 (en) 2007-04-03
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