Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
  • G11C7/14—Dummy cell management; Sense reference voltage generators
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/26—Sensing or reading circuits; Data output circuits
  • G11C16/28—Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
  • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
  • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
  • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
  • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
  • G11C29/24—Accessing extra cells, e.g. dummy cells or redundant cells
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
  • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
  • G11C29/50—Marginal testing, e.g. race, voltage or current testing
  • G11C29/50004—Marginal testing, e.g. race, voltage or current testing of threshold voltage
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
  • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
  • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
  • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
  • G11C29/38—Response verification devices
  • G11C29/40—Response verification devices using compression techniques
  • G11C2029/4002—Comparison of products, i.e. test results of chips or with golden chip

Definitions

• the present invention relates to memory devices and in particular, to a system and methods of programming reference cells in a flash memory device.
• a typical flash memory device includes an array of memory cells for the storage of data, a control circuit for handling the input, output, and storage of data, and a reference cell array for providing a set of reference standards each having a threshold voltage that has been precisely set by an external voltage setting machine.
• a typical flash memory cell is programmed by inducing hot electron injection from the channel region near the drain to the floating gate. Erasure of a flash memory cell is typically carried out by Fowler- Nordheim tunneling between the floating gate and the source or between the floating gate and the substrate. Either programming or erasure of a flash cell results in a non-volatile threshold voltage V t in the programmed or erased cell.
• the state of a selected memory cell is compared to a state of a reference cell in the reference array specifically programmed for the operation being performed. For instance, to determine whether a specific memory cell has been programmed or erased properly, the threshold voltage of a reference cell in the reference array is compared to the threshold voltage of a reference memory cell .
• a sensing circuit that resides in the control circuit is used to perform the voltage comparison between the memory cell and the reference cell .
• the reference cell array is typically composed of a set of reference cells each having a pre-programmed threshold voltage V t that is appropriate for a specific memory operation.
• the programming of the reference cells is typically performed by an external testing device.
• the external device machine sends a series of programming pulses to the reference cell to induce hot electron injection.
• the threshold voltage V t of the reference cell is then measured or read to determine if a desired threshold voltage V t has been achieved. If V t is below the desired value, more programming pulses are sent to the reference cell. This process of programming/ erasing and/or reading is repeated until the desired threshold voltage is reached.
• the repetitive process of programming, reading, and erasing of the reference cell is very time consuming.
• the most time intensive portion of the procedure is related to the reading step wherein a voltage is applied to the gate and drain of each reference cell and the resulting current is measured by the testing device using a direct memory access (DMA) method.
• DMA direct memory access
• the reference cell testing and setting time becomes very long.
• the number of reference cells increases significantly and the reference cells testing and setting time could become unacceptably high. Therefore, it would be desirable to have a system and method for testing and setting reference cells that significantly reduces the total testing and setting time.
• U.S. Patent No. 6,418,054 to Hollmer entitled “Embedded Methodology to Program/Erase Reference Cells used in Sensing Flash Cells” teaches a method of using internal circuits to set reference cells in UV (ultra violet) sensitive or UV erasable EPROMs.
• Such internally derived reference standards may be usable for certain memory devices.
• these internal reference setting mechanisms are susceptible to internal variations inherent in the memory chip and thus, they are not suitable for applications where highly precise reference standards are required.
• An example of such an application is a multilevel memory cell device that requires a fixed range of a multilevel threshold voltage distribution that has a very small tolerance. Therefore, it would also be desirable to have a reference setting system that can provide a set of highly precise reference thresholds .
• a system and method of programming memory reference cells that uses an embedded or an internal control circuit of a memory device, such as a flash memory or an EEPROM, to perform some of the time consuming portions of a cell programming process is described herein.
• an external testing device or other programming device is coupled to a memory device.
• the activity performed by the external testing device 24, as well as the activity by an internal control circuit 26 is shown.
• the procedure begins by applying power and initializing any parameters that may be used by the external testing device when programming cells within the memory device 23.
• the external testing device may be a circuit coupled to the memory device's pins or contact pads.
• the external testing device programs at least one reference cell within the memory device to a precise value, such as a threshold voltage value V t or a current value I 9 .
• golden cells programmed by the external testing device
• reference cells Other “non-golden” reference cells within the flash memory device
• the golden cell (s) will be used as a comparative standard to set other additional reference cells.
• the external testing device or other device instructs 25 an internal control circuit embedded within the memory device to begin setting other reference cells. For example, a latch may be set or a command may be sent to the internal control circuit, indicating that the external device has finished programming at least one golden cell and the internal control circuit should now begin to set or program other internal control reference cells.
• the reference cells are sequentially programmed 26 by the internal control circuit or alternatively, the reference cells may be simultaneously programmed by multiple sets of circuit inside the memory device. The internal control circuit then iteratively programs and compares the programmed reference cells to at least one of the golden cells.
• the reference cell programming operation is complete, and the internal control circuit ceases the reference cell programming operation 27.
• the iterative programming and comparison operation performed by the internal control circuit relieves the external testing device from the task of programming all of the required number of reference cells within the memory device.
• Figure 1 is a flow chart showing a general procedure of the present invention.
• Figure 2 is a block diagram showing an embodiment of the present invention.
• Figure 3 is a flow chart showing an algorithm for programming a plurality of reference cells according to the present invention.
• Figure 4 is an exemplary circuit that may be used to implement the flowchart illustrated in Figure
• Figure 5 illustrates ideal voltage and current characteristics for two exemplary reference cells .
• Figure 6 illustrates actual voltage and current characteristics for two exemplary reference cells.
• flash memory device 10 has a memory cell array 12.
• the memory cell array 12 is comprised of a plurality of flash memory cells (not shown) .
• Programming, reading, and erasing reference memory cells in the memory cell array 12 is carried out by an internal control circuit 14.
• the internal control circuit 14 contains state machine logic (not shown) for the execution of various memory accessing functions, a plurality of sensing circuits (not shown) for the reading of the memory cells, a plurality of addressing logic units for the proper selection of memory cells, and a plurality of input/output logic units (not shown) for the input and output of data.
• a group of reference cells 20 provide standard references for comparison to other memory cells in the memory cell array.
• a golden cell 22 provides a precise, optimal, and predefined reference or absolute threshold value that may be used to set or program at least one additional reference cell.
• An external testing device 16 connects to a golden cell 22 that will be used later as a standard comparative cell when programming at least one other reference cell .
• the external testing device 16 programs at least one golden cell 22 to a specific threshold voltage by repeating the steps of sending programming pulses to the golden cell 22 and then measuring a resulting threshold voltage using a direct memory access DMA method.
• the golden cell 22 may be fully programmed/erased using controlled program/erase pulses to set a threshold voltage.
• this step of establishing a golden voltage is used to establish an accurate reference for later setting a group of additional reference cells 20.
• the external testing device 16 uses a starting program voltage, programming pulses, steps between pulses, and voltage verification) has set the required number of golden cells, the external testing device 16, does not set the other additional reference cells 20.
• the external testing device 16 instructs the internal control circuit 14 that the internal control circuit 14 may begin to set at least one internal reference cell 20.
• the external testing device 16 may provide a command to the internal control circuit 14, or set a latch or line to a pre-determined logic value.
• the external testing device 16 After the external testing device 16 has provided a command to the internal control circuit 14 to begin, the external testing device 16 no longer sets any reference cell (s) 20.
• the internal control circuit 14 then uses at least one programmed golden cell 22 as a standard comparative reference to set or program at least one reference cell (s) 20 within the memory device.
• the internal reference cell (s) 20 to be set may be selected from the group of reference cells 20 embedded in the memory device 10 and may be programmed individually (one at a time) or simultaneously.
• a reference cell may be changed to obtain a target threshold value V M using a target voltage threshold, or by using a target current setting means I m .
• the internal control circuit performs a current comparison between the golden cell 22 and a single reference cell 20.
• multiple reference cell currents may be verified and compared with a pre-programmed golden cell.
• an embodiment of a voltage threshold setting procedure for a selected reference cell 55 may be implemented by programming a single reference cell or serially programming multiple reference cells one-by-one. For programming a single reference cell, only a single sense circuit 58 and a single indicator line 59 is required.
• the sense amplifier, for each reference cell 55 will verify that:
• V th i is the target threshold for the reference cell being set
• V tg is the threshold of the golden cell.
• a gate voltage of a golden cell 50 may be different than a gate voltage of the selected reference cell 55.
• buffers (not shown) in the internal control circuit 14 are loaded with a set of desired threshold voltage values ranging from V ref i to Vrefm/ where variable m refers to a number of corresponding reference cells to be set.
• a counter 30 that keeps track of the number of reference cells is reset to an initial value. For instance, the counter may be reset to 1 at the beginning of each programming routine to indicate that a first reference cell within the group of reference cells 20 is to be programmed. Based on the target threshold voltage Vi for the first reference cell, a start programming voltage value is loaded 32 into a programming circuit that resides in the internal control circuit 14.
• the threshold voltage of the first reference cell may be verified 34 using an internal control circuit that is similar to those used for sensing normal memory cells.
• the operation matches a particular reference cell to a pre-set golden cell by comparing 36 the reference cell's measured threshold voltage with the target cell threshold voltage value Vi.
• the algorithm proceeds to increase a gate voltage to a value higher than the previously applied voltage, such as 0.125 Volts higher from an exemplary 4.0 Volts to 4.125 Volts, and sends an additional programming pulse to the first reference cell 40.
• the threshold voltage of the first reference cell is then verified 34 again. Once the target threshold voltage is reached, the reference cell is properly programmed. If the measured threshold voltage of the first reference cell matches that of the target threshold voltage value Vi stored in the buffer, then the algorithm proceeds to check whether more reference cells are to be programmed.
• the cell counter is incremented 44 and the next reference cell is then programmed. If the last reference cell has been programmed, a determination 42 is made that the end count has been reached, and the threshold voltage setting algorithm is terminated (done) .
• verification and comparison operations of a reference cell may be implemented.
• the threshold of the reference cell may be changed to obtain a target threshold value V m using a target current I M to set the reference cell. Similar to the steps in Figure 3, the steps to verify 34 a threshold setting and subsequent steps 36-44 may be implemented by performing a current comparison between a reference cell and a golden cell.
• an internal control circuit performs a current comparison 36 between the golden cell current, with a predetermined or fixed voltage applied to the golden cell gate (usually the read voltage) , and each reference cell current (or its ratio) , with the same predetermined or fixed voltage applied to each reference cell gate.
• the golden cell current I g will be measured and compared 36 with reference cell (s) current using a selected or predetermined word line supply voltage.
• the reference cell (s) current will be measured using a particular gate voltage V 9 .
• a reference cell 20 may be set using an internal control circuit 14. Reference cell 20 characteristics are compared to the programmed golden cell 22, using voltage threshold V tg , or cell current.
• a golden cell 22 is typically pre-programmed by an external testing device 16 to a defined voltage threshold Vtg.
• a particular voltage threshold Vtg for the golden cell 22 is associated with a particular current threshold I th that is chosen to define the voltage threshold value of a cell.
• the golden cell is defined to have a threshold V tg if it sinks a pre-chosen current (I t h) when its gate is V tg .
• This current I th/ used to define a voltage threshold is usually a very low current, for example, IuA to 2uA.
• the current value may be chosen to define a voltage flash threshold using lua I th current, so that golden cell may have a threshold of 2 Volts only when it sinks IuA when the gate voltage is 2 Volts.
• an I 9 (gate) current comparison is defined, and is set at a chosen fixed gate voltage value, normally equal to the read mode gate voltage.
• the golden current comparison I 9 may be defined using chosen voltage parameters, for example 20 microamps, when its gate is equal to a read gate value V xr .
• the V xr value may be pre-programmed by the external testing device 16 into a golden cell 22.
• a comparison may be made between a golden cell 22 current I g , or a multiple or fraction of I 9 , and a single reference cell current I re fM while applying a predetermined voltage (VT rM ) value, that is stored in a load programming value 32 register, to both the gate of the golden cell 22 (shown in Figure 2) and to the gate of a reference cell 20 (shown in Figure 2) .
• VT rM predetermined voltage
• a current verification is performed 34 on the reference cell 20, followed by a comparison 36 between the golden cell current I 9 (or a multiple or fraction of I 9 ) and the reference cell current I re fM- If IrefM > Ig (or a multiple or fraction of I 9 ) , then the desired programmed threshold set for the reference cell is not desirable, and must be changed.
• additional adjustment pulses are sent 40 until the desired condition occurs where the golden cell current I 9 (or a multiple or fraction of I 9 ) is equal to the reference cell current Ire fM -
• the reference cell will continue to be programmed (or erased) until the current threshold in the reference cell is equal to the current threshold (or a multiple or fraction of I 9 ) in the golden cell.
• the external testing device 16 programs the golden cell 22 to a particular current value I C urr e nt a t a particular read voltage V rea d-
• a particular reference cell current IrefM is loaded 30 into the programming value register. This current value is the desired reference cell current when the reference cell gate is equal to the read voltage V read of the golden cell 22.
• reference cell current is the desired reference cell current when the reference cell gate is equal to the read voltage V read of the golden cell 22.
• Ir efM may be set at a fraction or multiple of a golden cell current I 9 .
• the golden cell 22 may be set to sink I 9 when a read voltage V rea d (V xr ) is applied to its gate.
• An exemplary circuit of Figure 4A performs a current verification and/or comparison between a golden cell 50 and at least one reference cell 55.
• a verify control gate voltage V xr is applied to at least one golden cell 50.
• the same value of gate voltage is applied to at least one reference cell 55.
• the gate voltage is applied to at least one word line.
• the golden cell gate voltage V gs and the reference cell gate voltage will be equal to a read voltage V rea( ⁇ in the current threshold method.
• a sense circuit 58 monitors the drain current of the golden cell 50 and the drain current (s) of at least one reference cell 55.
• the sense circuit 58 compares the golden cell drain current with the drain current of at least one reference cell 55. If the current value from the golden cell 50 matches the current value from at least one reference cell (or a ratio, see below) , the sense circuit 58, relative to the matching reference, will provide a signal on an indicator line 59 indicating that the current values match. Referring to Figure 3, if the current values (or a multiple or fraction) do not match, a program pulse will be sent 40 to at least one reference cell 20 not yet matching a target current until the current values match the target currents. Referring to Figure 4B, at least one ratio
• coefficient value Ri, R 2 ,... R M may be used for each reference cell 55, -55 M such that using a current method to set multiple reference cells in parallel :
• the ratio circuitry 52 is set for a selected number of reference cells so that the target output currents I g Ri, I 9 R 2 , ... IgRM are set.
• An M (multiple) number of sense circuits 58 are used to sense the currents Ri * I g oiden_ceii to set M references in parallel.
• each sense amplifier when setting multiple reference cells, each sense amplifier will provide an indication when each cell has been properly programmed, for example by toggling an indicator line 59 that exists for each reference cell that is being set. In one embodiment, if all the reference cells are not correctly set, then the next program pulse will only be applied to those reference cells that are not correctly set. A reference cell setting procedure ends when all the targeted reference cells have been correctly set. Applying the coefficient to a plurality of reference cells 55i - 55 M allows a single golden cell 50 to be compared with more than one reference cell 55i - 55 M in a single current comparison operation. The ratio coefficient value R ⁇ may multiply or apply a fraction to the current value of each reference cell 55.
• thirty-two reference cells 55 may be measured in one operation, with the ratio coefficient Ri applied to at least one ratio device 52 ⁇ to 52 M .
• the current in each reference cell 55 (i) is equal to the current I 9 (in the gold cell) divided by the corresponding reference coefficient Ri, such that
• a verify voltage V ve ri f y 101 is greater than any of the threshold voltages V t h_r e fm 110, 120 of the referenced cells when performing a verify or read operation.
• the voltage threshold V th of a reference cell V t h_ ref i HO is lower than the voltage threshold of another reference cell V th re f 2/ 120, the current for the first reference cell I r e f i Hl will be higher than the current for the second reference cell I r ef2 121.
• each reference cell will maintain the same change in voltage and current when erased and programmed, and will provide reliable results during a read or verify operation using a verify voltage V ver i fy 101.
• a reference cell When changing the threshold voltage for either reference cell, a reference cell will track the other reference cell's threshold voltage and current, and a generic memory cell may be correctly erased, programmed, or read using either reference cell.
• Reference cells having the same gain provides uniform performance of all the reference cells in a memory device. It is desirable to avoid different gains between the reference cells, however, it is difficult to match the gains of all reference cells and generic memory cells within a memory array.
• a distribution of gains and a distribution of thresholds are the normal outcome for a memory array manufacturing process.
• a mismatch of the gains of reference cells reduces the current margin allowed to correctly read a logic value of a particular generic memory cell within a memory array.
• a verify voltage Vverify 201 is greater than the threshold voltages V t h_refm 210, 220 of the reference cells when performing a verify operation.
• the voltage threshold V th. of a reference cell V t h_refi 210 is lower than the voltage threshold of another reference cell V t h_ref2/ 220, the current for the first reference cell I re fi 211 may be less than the current for the second reference cell I re fi 221 during a verify operation. This difference between the gain of the reference cells may cause an incorrect read or verify value.
• V ve rify as a read or verify voltage and the voltage-current line for V th _ ref2 220 as a reference
• a cell having the voltage current characteristics associated with V t h r efi 210 would be read as a logic value 0 instead of an intended logic value of 1 because I re fi ⁇ Iref2•
• using a verify voltage that exceeds V* 230 will produce a reference cell margin that is too narrow and may incorrectly read the logic value of another cell.
• a golden cell may be precisely set to a particular current value to reduce read failures due to differences in gain of the reference cells.
• the invention relieves the external testing device 16 from having to program all the reference cells 20 within the memory device 10.
• M is the number of reference cells to be set and Ci denotes the i-th reference cell, where 1 ⁇ i ⁇ M.
• C r denotes the golden cell
• N is the average number of programming pulses used for setting each cell
• T se t_cr is the total time for setting the golden cell
• T set _ci is the total time for setting the i th reference cell .
• T prOg is the time for sending a programming pulse
• T DMA is the time for dynamic memory access from the external testing device.
• T DMA 50 ms
• T prOg 1 ms
• M 20
• ⁇ 10
• the T to t_test_device is about 10 10 seconds.
• T ver _ertib is the time for verifying the threshold voltage using an internal control circuit
• T ver _ e m b is negligible with respect to a T DMA of 50 ms to 100 ms. 20
• the total time T tot _ e ⁇ i b for setting all the reference cells in the memory device is
• T tot _ era b is now only about 0.5 seconds. As a result, a total time for the external test device to program all of the reference cells within the memory device is greatly reduced.
• the time savings may be multiplied by the number of dies simultaneously tested.

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• 2005
  • 2005-11-18 WO PCT/US2005/042083 patent/WO2006071402A1/en not_active Ceased
  • 2005-11-18 EP EP05848820A patent/EP1831892A4/de not_active Withdrawn

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