Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/711—Insulated-gate field-effect transistors [IGFET] having floating bodies
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
  • H10D30/691—IGFETs having charge trapping gate insulators, e.g. MNOS transistors having more than two programming levels
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/751—Insulated-gate field-effect transistors [IGFET] having composition variations in the channel regions
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/01—Manufacture or treatment
  • H10D62/021—Forming source or drain recesses by etching e.g. recessing by etching and then refilling
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/113—Isolations within a component, i.e. internal isolations
  • H10D62/115—Dielectric isolations, e.g. air gaps
  • H10D62/116—Dielectric isolations, e.g. air gaps adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
  • H10D62/351—Substrate regions of field-effect devices
  • H10D62/357—Substrate regions of field-effect devices of FETs
  • H10D62/364—Substrate regions of field-effect devices of FETs of IGFETs
  • H10D62/371—Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/0413—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having charge-trapping gate insulators, e.g. MNOS transistors

Definitions

• the present invention relates to the field of transis ⁇ tors MOS and memory points integrated circuit. Discussion of the Related Art In the field of integrated memory cells, known in particular MOS dual gate transistors in the ⁇ what a load is likely to be stored in a floating gate, which changes the characteristics of the MOS transistor. MNOS-type components are also known in which charges are likely to be stored in an insulator, preferably at the interface between two insulators such as oxide and silicon nitride.
• Memory points consisting of MOS transistors comprising, under their channel region, a conductive zone completely surrounded by insulators are also known (see Ranica et al., "A new 40-nm SONOS structure based on backside trapping for nanoscale memories", IEEE Transactions on Nanotechnology, Vol. 4, N 0 5, September 2005, PP. 581-587). Summary of the invention
• the present invention aims to provide a modifiable threshold MOS transistor that can constitute a memory point
• the present invention provides a MOS transistor comprising a conductive extension of its source region, isolated from its substrate, and extending partially under its channel.
• the isolated extension extends over a length equal to a distance of about one-quarter to one-third of the channel length.
• said extension is made of polycrystalline silicon.
• the isolation of said extension is performed by a multilayer structure such as a silicon nitride and silicon oxide bilayer.
• the present invention also provides a method of programming a memory point consisting of a MOS transistor as above, consisting in circulating a current from the source to the drain, whereby carriers are trapped in the insulation of said extension.
• a method of erasing a programmed memory point consists, while the transistor is not put in the conducting state, to polarize the source so as to extract the charges trapped in the insulator.
• the present invention also provides a method of manufacturing a transistor comprising, under a monocrystalline silicon layer, a layer selectively etchable with respect to this monocrystalline silicon layer, said method comprising the steps of forming a gate structure; anisotropically etching the silicon layer mono ⁇ lens and selectively etchable layer, using the gate structure as a mask; etching the selectively etchable layer laterally; filling the removed portions of the selectively etchable layer of insulation and a conductor; and forming source and drain regions, the source region being in contact with said conductor.
• the selectively etchable layer is a monocrystalline silicon-germanium layer formed on monocrystalline silicon.
• FIG. in very schematic section of an MOS transistor with modifiable threshold according to the present invention
• FIGS. 2A to 2E are sectional views illustrating successive steps of manufacturing a MOS transistor according to an embodiment of the present invention
• FIG. 3 shows an example of MOS transistor obtained by the method illustrated in FIGS. 2A to 2E.
• FIG. 1 very schematically shows a modified conventional MOS transistor structure according to the present invention.
• the conventional MOS transistor comprises strongly doped source and drain regions 1 and 2 of a first conductivity type, for example N + , separated by a region 3 of the opposite conductivity type.
• a channel may be formed under the effect of a conductive grid 5 isolated from the channel by a thin insulating layer 6.
• the grid is surrounded by spacers 7 under which formed of lightly doped source and drain extensions 8 and 9 (LDD) of the same conductivity type as the source and the drain.
• LDD lightly doped source and drain extensions 8 and 9
• This transistor is capable of the various variants commonly used for the realization of MOS transistors and among which may be mentioned as examples the following:
• the grid 5 may be made of polycrystalline silicon, polycrystalline silicon surmounted by a silicide layer, or even be completely silicided,
• the gate 5 may be metallic, the upper parts of the source and drain regions 1 and 2 may be silicided,
• the transistor can be produced, as shown, on a solid silicon substrate, or on a silicon layer resting on an insulating layer (SOI), each transistor is separated from the neighboring transistors by one or the other various known techniques, for example by producing an insulating layer up to the deep insulating layer in the case of an SOI type structure, or, in the case of a massive silicon structure, by transitions equipped with insulation, for example to achieve se- parations between STI (shallow trench insulation) transistors,
• the MOS transistor will for example have a gate length of 65 nm, the spacers protruding about 30 nm from the grid.
• the present invention provides to modify such a conventional MOS transistor by adding the side of its source a conductive finger 10 extending under a portion of the length of the channel of the transistor and surrounded by a layer of at least one insulating mate ⁇ riau 11.
• the conductive finger 10 extends for example over a length of one quarter to one third of the length of the channel of the transistor. It will be understood that, in the width direction, this finger extends substantially over the width of the grid.
• the finger 10 will have a length from the source of at least 50 nm, so as to extend under the channel beyond the d-zone.
• Source extension 8 This finger will be at a depth relative to the gate insulator 6 of about 10 nm.
• the MOS transistor In the normal state, for a depletion N-channel MOS transistor, when the drain is positively biased with respect to the source and the gate is positively polarized, a current flows from the drain to the source (the electrons go from the source to the drain). If the MOS transistor is used in memory point, this operating mode is said read mode.
• the source may be grounded, the drain at a low voltage, for example 0.1 volts, and the gate at a voltage of 0.5 to 1 volt.
• the substrate in which the tran ⁇ sistor is formed and in the upper part of which the channel is formed is preferably biased to ground. For this, the entire substrate is connected to the ground in the case of a solid substrate. We can also find various ways to polarize the substrate in the case where it is a portion of silicon layer on an insulating layer.
• the drain is grounded and the source is set to a potential of the order of 1 to 1.5 volts for a transistor having the dimensions indicated above, the gate being set to a positive potential.
• the transistor operates in a mirror manner, that is to say that the current flows from its source to its drain or that the charge carriers, the electrons for an N-channel transistor, flow from the drain to the source.
• the electrons are attracted, at least in part, by the conducting finger 10 and electrons are trapped in the insulator 11.
• this insulator consists of a bilayer of insulators having different forbidden bands, such as a silicon nitride and silicon oxide bilayer, the electrons trap extremely stably at the interface between the two insulating layers.
• the drain and the gate (as well as the substrate) are placed at a reference potential, commonly the mass, and a positive potential is applied to the source. Then, it attracts the electrons that are trapped in the insulation, or at the interface between the insulators, surrounding the conductive finger.
• a reference potential commonly the mass
• a positive potential is applied to the source. Then, it attracts the electrons that are trapped in the insulation, or at the interface between the insulators, surrounding the conductive finger.
• high voltages are not required and that voltages of the order of 1 to 1.5 volts are clearly sufficient.
• Tests and simulations have shown that with a transistor having dimensions of the order of those indicated above, a reading current is obtained for a given drain-source voltage and for a given gate voltage. 10 times larger in the unprogrammed state than in the programmed state.
• the two states according to the present invention are clearly discernible.
• the device according to the invention has the advantages of requiring low power and low voltages for its reading, programming and erasure.
• the device according to the invention has the advan tage ⁇ a large charge retentive period (possibly several years) without cooling.
• the state of the device according to the invention can be switched very quickly and this device is achievable in very small dimensions.
• a dispo ⁇ sitive according to the invention is compatible with current methods of manufacturing CMOS transistors and does not add a manufacturing step with respect to the production of such transistors, especially in the framework of manufacturing processes in which a step of forming a silicon-germanium layer is used.
• An exemplary embodiment of a transistor according to the present invention will now be described by way of example only with reference to FIGS. 2A to 2E.
• two fingers are formed extending respectively from the source and the drain, but, as has been explained previously, only the source finger is used (using the conventional source and drain definition of a MOS transistor).
• a substrate portion containing successively a monocrystalline silicon layer 20, a monocrystalline silicon-germanium layer 21 and a monocrystalline silicon layer 22 is formed on a grid structure comprising a grid 5 on a gate insulator 6.
• the gate is surrounded by a spacer 7.
• the silicon-germanium layer 21 may have a thickness of the order of 10 to 20 nm, likewise than the upper monocrystalline silicon layer 22.
• the gate structure of FIG. 2A was used as a mask for successively anisotropically etching the silicon layer 22, the silicon-germanium layer 21 and possibly a small thickness of the layer of silicon.
• lower silicon 20 is the upper part of a monocrystalline silicon wafer or a silicon on insulator layer resting on a silicon wafer according to the well-known SOI technique, or the like.
• the silicon-germanium is selectively etched, this etching can be an isotropic etching and makes it possible to reduce the length of the silicon-germanium layer 21 to leave a portion of silicon-germanium 21 in place. germanium 24 of shorter length than the length of the grid 5. There are then openings 25 between the two silicon layers 20 and 22 on both sides of the grid.
• the insulating layer 27 can result from thermal oxyda ⁇ tion (silicon oxide) and d a deposit of silicon nitride. This or these insulating layers may be of other materials, for example silicon nanocrystals, nitride, germanium, multilayer insulants.
• the conductive layer 28 can be polycrystalline silicon, amorphous or monocrystalline. Various methods known in the art can be used to deposit and then dispose of the filler materials used outside the openings. For example, it will be possible to make conformal deposits over the entire surface of the component and then to etch.
• FIG. 3 The structure obtained is illustrated in FIG. 3 in which like references refer to the same elements as in FIGS. 2A to 2E. Insulating trenches 30 delimiting the active zone in which the transistor according to the invention is formed are also shown. The structure is coated with an insulating layer 31 through which vias 32 and 33 for making source and drain contacts are formed. In addition, silicide layers 33, 34 and 35 are shown above the source, the drain and the grid. The gate contact is not shown and is taken up laterally in a conventional manner.
• the present invention has been described in the context of an application to the realization of a two-state memory point.
• the device described more generally consists of a MOS transistor with adjustable threshold according to the amount of charges injected into the insulator of a conductive finger penetrating under its gate. And this MOS transistor adjustable threshold can find other applications.
• Transistors according to the present invention can be assembled into a matrix network. They can also be elements of a network of logic gates.

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• Thin Film Transistor (AREA)
• Semiconductor Memories (AREA)
• Non-Volatile Memory (AREA)
• Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

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• 2007
  • 2007-02-14 WO PCT/FR2007/050798 patent/WO2007093741A2/fr not_active Ceased
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