EP2047525A2 - Composant semi-conducteur a couche mince et lien de composant - Google Patents

Composant semi-conducteur a couche mince et lien de composant

Info

Publication number
EP2047525A2
EP2047525A2 EP07785643A EP07785643A EP2047525A2 EP 2047525 A2 EP2047525 A2 EP 2047525A2 EP 07785643 A EP07785643 A EP 07785643A EP 07785643 A EP07785643 A EP 07785643A EP 2047525 A2 EP2047525 A2 EP 2047525A2
Authority
EP
European Patent Office
Prior art keywords
layer
thin
film semiconductor
semiconductor device
heat dissipation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP07785643A
Other languages
German (de)
English (en)
Inventor
Siegfried Herrmann
Berthold Hahn
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ams Osram International GmbH
Original Assignee
Osram Opto Semiconductors GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Osram Opto Semiconductors GmbH filed Critical Osram Opto Semiconductors GmbH
Publication of EP2047525A2 publication Critical patent/EP2047525A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
    • H10H20/018—Bonding of wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/858—Means for heat extraction or cooling
    • H10H20/8582—Means for heat extraction or cooling characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/858—Means for heat extraction or cooling
    • H10H20/8585—Means for heat extraction or cooling being an interconnection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/83—Electrodes
    • H10H20/831—Electrodes characterised by their shape
    • H10H20/8314—Electrodes characterised by their shape extending at least partially onto an outer side surface of the bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/852—Encapsulations
    • H10H20/853—Encapsulations characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/857—Interconnections, e.g. lead-frames, bond wires or solder balls
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H29/00—Integrated devices, or assemblies of multiple devices, comprising at least one light-emitting semiconductor element covered by group H10H20/00
    • H10H29/10—Integrated devices comprising at least one light-emitting semiconductor component covered by group H10H20/00

Definitions

  • the optical structure can be arranged on a side of the cover layer facing or facing away from the layer stack.
  • a two-sided arrangement of the carrier layer and the cover layer can advantageously replace a housing body.
  • a contact pad for an outcoupling-side electrical contact of the layer stacks on the carrier layer is applied between the layer stacks.
  • the thin-film semiconductor devices may be electrically connected in various ways.
  • the thin-film semiconductor devices are connected in series.
  • the second connection region of a first thin-film semiconductor component for example by means of a bonding wire, is particularly preferably electrically connected to the heat-dissipation layer of a second thin-film semiconductor component, the heat-dissipation layer serving as an electrical contact.
  • the first and the second connection region may be arranged on a side of the layer stack facing the carrier layer, wherein the first connection region is electrically connected to a first heat-dissipating layer serving as electrical contact and the second connection region is electrically connected to a second heat-dissipating layer serving as electrical contact.
  • Figure 3 is a schematic sectional view of a second. ' .
  • Embodiment of a thin-film semiconductor device according to the invention
  • FIG. 4 shows a schematic sectional view of a third exemplary embodiment of a thin-film semiconductor component according to the invention
  • FIG. 7 shows a schematic top view of a first exemplary embodiment of a component composite according to the invention
  • Figure 9 is a schematic cross-sectional view of a fourth embodiment of a device composite according to the invention.
  • Figure 10 is a schematic cross-sectional view of a fifth embodiment of a device composite according to the invention.
  • the same or equivalent components are each provided with the same reference numerals.
  • the illustrated components of the figures, in particular the sizes of layer thicknesses shown, are in principle not to be regarded as true to scale. Rather, they can be exaggerated in size for clarity.
  • the cover layer 10 is suitable as electrical insulation between a heat dissipation layer 3 and a conductor 9.
  • the heat dissipation layer 3 can have electrical conductivity in addition to the thermal conductivity.
  • a passivation layer 7 is arranged between the conductor track 9 and the semiconductor layer sequence 5. This contains, for example, silicon oxide.
  • the layer sequence 5 is provided essentially for generating radiation.
  • the layer sequence 5 can have a conventional pn junction, a double heterostructure, a single quantum well structure or a multiple quantum well structure.
  • the layer sequence 5 is substrateless, which means that a growth substrate used for growing the layer sequence 5 is no longer present in the finished thin-film semiconductor component 1.
  • the layer stack 8 (see Figure 2) comprises a first electrical connection region 5 and a second electrical connection region 6, which is arranged radiation output side.
  • the layer stack 8 is arranged on a carrier layer 2 which has a heat dissipation layer 3.
  • the carrier layer 2 is a film on which the heat dissipation layer 3 is patterned before the layer stack 8 is mounted on the heat dissipation layer 3.
  • the layer stack 8 is bonded to the heat dissipation layer 3.
  • the thickness D w of the heat dissipation layer 3 is preferably between 5 ⁇ m and 30 ⁇ m, with a metal, for example Cu, Ni or Ag, being particularly suitable as the material.
  • the thickness D 3 of the layer sequence 5 and of the first electrical connection region 4, which is approximately 7 ⁇ m, can thus be less than the thickness D w of the heat dissipation layer 3.
  • the small thicknesses of the carrier layer 2, the slaughterableit ⁇ ngsSchicht 3 and the layer stack 8 allow a total of a thin-film semiconductor device • 1 low overall height. It is a height D ges achievable, which is preferably less than 100 ⁇ m.
  • the combination of carrier layer 2 and cover layer 10, which replace a housing body or form a housing for the thin-film semiconductor component 1, also contributes to this.
  • the low height of a single thin-film semiconductor device 1 allows stacking of a plurality of thin-film semiconductor devices, whereby the luminance can be increased.
  • the heat dissipation layer 3 completely covers a base area of the layer stack 8.
  • the heat dissipation layer 3 it is also possible for the heat dissipation layer 3 to be offset from the layer stack, so that the radiation emitted by the layer sequence reaches the carrier layer 2 directly.
  • the conductor 9, which is provided for a second electrical connection, preferably runs in steps.
  • the conductor track from the first electrical connection region 6 is guided along a radiation decoupling surface 11 over a side surface of the layer stack 8 onto the carrier layer 2.
  • the heat dissipation layer 3 and the conductor 9 are opposite the backing layer 2 or the covering layer 10 in the lateral direction in such a way shows that its electrical connection to a power supply 'is possible in a simple manner.
  • the carrier layer 2 has a first partial layer 2 a and a second partial layer 2 b.
  • the first 'part layer 2a is a thin layer, the thickness of the Partial layer 2a is chosen such that a relatively high heat flow is possible. The heat flow is antiproportional to the layer thickness.
  • the thickness of the sub-layer 2a is in the single-digit micrometer range.
  • the partial layer 2 a is electrically insulating and in particular contains a plastic material.
  • both the conductor track 9 and the heat dissipation layer 3 can be applied to the carrier layer 2, without these being short-circuited.
  • the heat dissipation layer 3 may be formed of a system of electrodeposited layers.
  • the second sub-layer 2b is a film, preferably a metal foil containing copper, for example, is provided.
  • a good heat transfer is possible.
  • a strong expansion of the second sub-layer 2b due to the heating can be advantageously counteracted by the first sub-layer 2a, which has a lower thermal expansion coefficient than the second sub-layer 2b.
  • the carrier layer 2 is arranged on a base 15.
  • the pad 15 advantageously has a good thermal conductivity.
  • the pad 15 is a metal foil.
  • the carrier layer 2, however, may be a plastic film.
  • a carrier layer 2 made of paper is conceivable.
  • a thermal compound is used for the mechanical and thermal connection of the carrier layer 2 to the substrate 15.
  • the thin-film component 1 shown schematically in plan view in FIG. 5 comprises a carrier layer 2 on which the heat-dissipation layer 3 and the layer stack
  • the second electrical connection region 6 and the conductor 9 expediently contain an electrically conductive material.
  • This may be a metal or a TCO (Transparent Conductive Oxide).
  • the carrier layer 2 may be electrically conductive, so that it makes sense to remove the carrier layer 2 in the region between the heat dissipation layer 3 and the contact pad 12 in order to avoid a short circuit during operation of the thin-film semiconductor component 1.
  • the thin-film semiconductor component 1 can be soldered or glued onto a printed circuit board in accordance with an SMT component with the structured carrier layer 2.
  • the component composite 13 shown in FIG. 7 has a plurality of layer stacks 8, which are preferably designed as described in more detail in connection with FIGS. 2 and 6.
  • the stack of layers 8 are anuß.- on a common carrier layer 2 Further, the stack of layers 8 are connected by means of the conductor tracks 9 to a common 'contact pad 12, which is arranged on the carrier layer. 2
  • the size of the device array 13 can be varied by simply dicing the device array 13.
  • the component composite 13 is particularly suitable for backlighting and lighting purposes.
  • component circuits 13 are shown, which have a plurality of thin-film semiconductor devices 1.
  • the thin-film semiconductor components 1 each comprise a layer stack 8 and a part of the common carrier layer 2, on which the layer stacks 8 are arranged.
  • a heat dissipation layer 3 which serves here except for cooling as an electrical contact.
  • a bonding wire 14 leads to the rear side disposed heat dissipation layer 3 of a second thin film semiconductor device 1 adjacent to the first thin film semiconductor device 1.
  • the two thin film semiconductor devices 1 are connected in series.
  • the number of series-connected thin-film semiconductor components 1 can be chosen arbitrarily large due to the application.
  • the layer stacks 8 are arranged in a decentralized manner on the respective heat dissipation layer 3, as a result of which an improved front-side contacting of the layer stacks 8 is possible in comparison to a central arrangement.
  • the base of the heat-dissipating layer 3 is formed like a scale and has in particular a recessed side edge and a side edge thereof opposite bulged.
  • the layer stack 8 is preferably arranged on the indented side edge, since the current injection is better here than in the bulged side edge.
  • part of the heat dissipation layers 3 may be free of layer stacks 8.
  • the unpopulated heat dissipation layers 3 are preferably integrated into the series connection, so that advantageously also a layer stack 8 surrounded by unpopulated heat dissipation layers 3 can be supplied with electrical comparatively simple.
  • FIG. 8c shows a cross-sectional view of the component composite 13 already described in connection with FIG. 8a.
  • the component composite 13 comprises a plurality of layer stacks 8, which are arranged on a common carrier layer 2 and are each mechanically and electrically connected to a first heat dissipation layer 3 and a second heat dissipation layer 3 adjacent to the first heat dissipation layer 3. are connected. Both electrical contacts are in this case on the .jesper heat dissipation layers 3 facing side of the layer stack 8.
  • a complete connection of the layer stacks 8 can take place by means of a complete bridging of adjacent heat dissipation layers 3 by means of a plurality of layer stacks 8.
  • both electrical contacts of the layer stacks 8 are arranged on the side facing the carrier layer 2.
  • the carrier layer 2 contains in this case electrically insulating material, in particular a plastic material, and further comprises openings for plated-through holes.
  • the carrier layer 2 is a plastic film.
  • the base 15, with which the carrier layer 2 is mechanically and thermally connected, is preferably a metal foil, so that a first electrical connection of the layer stacks 8 takes place by means of the base 15.
  • a second electrical connection of the layer stacks 8 is possible by means of the heat dissipation layer (not shown) applied to the carrier layer 2.
  • the methods for wireless contacting used in the invention require no. adjusted bonding process. Furthermore, the arrangement of the heat dissipation layer serving as a conductor track and the further conductor track on one side of the component enables a simple contacting of the thin-film semiconductor component.

Landscapes

  • Led Device Packages (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Laminated Bodies (AREA)

Abstract

L'invention concerne un composant semi-conducteur à couche mince avec une couche de support et un empilement de couches disposé sur la couche de support, lequel contient un matériau semi-conducteur et sert à émettre un rayonnement. Une couche de dissipation thermique pour refroidir le composant semi-conducteur est appliquée sur la couche de support. L'invention concerne en outre un lien de composant.
EP07785643A 2006-08-04 2007-07-16 Composant semi-conducteur a couche mince et lien de composant Withdrawn EP2047525A2 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE102006036543 2006-08-04
DE102007004303A DE102007004303A1 (de) 2006-08-04 2007-01-29 Dünnfilm-Halbleiterbauelement und Bauelement-Verbund
PCT/DE2007/001273 WO2008014750A2 (fr) 2006-08-04 2007-07-16 Composant semi-conducteur à couche mince et lien de composant

Publications (1)

Publication Number Publication Date
EP2047525A2 true EP2047525A2 (fr) 2009-04-15

Family

ID=38596017

Family Applications (1)

Application Number Title Priority Date Filing Date
EP07785643A Withdrawn EP2047525A2 (fr) 2006-08-04 2007-07-16 Composant semi-conducteur a couche mince et lien de composant

Country Status (8)

Country Link
US (1) US8872330B2 (fr)
EP (1) EP2047525A2 (fr)
JP (1) JP5517616B2 (fr)
KR (1) KR101386303B1 (fr)
CN (1) CN101542752B (fr)
DE (1) DE102007004303A1 (fr)
TW (1) TWI378571B (fr)
WO (1) WO2008014750A2 (fr)

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TW200816524A (en) 2008-04-01
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CN101542752B (zh) 2014-01-22
CN101542752A (zh) 2009-09-23
KR20090035040A (ko) 2009-04-08
JP5517616B2 (ja) 2014-06-11
WO2008014750A2 (fr) 2008-02-07
JP2009545863A (ja) 2009-12-24
TWI378571B (en) 2012-12-01
US8872330B2 (en) 2014-10-28
US20100163915A1 (en) 2010-07-01

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