Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N60/00—Superconducting devices
  • H10N60/20—Permanent superconducting devices
  • H10N60/205—Permanent superconducting devices having three or more electrodes, e.g. transistor-like structures 
  • H10N60/207—Field effect devices

Definitions

• the present invention relates to a superconductive field effect transistor of the type comprising a source electrode and a drain electrode, connected by a superconducting channel, the channel and the source and drain electrodes being disposed on a substrate, and a grid covering the canal.
• the invention also relates to a method for manufacturing a field-effect superconductive transistor, said transistor comprising a source electrode and a drain electrode, connected by a superconducting channel, the channel and the source and drain electrodes being disposed on a substrate, and a gate electrode covering the channel.
• EP 0 505 259 discloses a superconductive field effect transistor comprising a substrate and a multilayer structure defining a channel and disposed on the substrate.
• the transistor comprises a source electrode and a drain electrode connected by the channel.
• the channel is controlled by a gate electrode, between a blocked state in which current does not flow substantially between the source electrode and the drain electrode, and a conducting state in which current flows from the source electrode. to the drain electrode.
• the amount of current flowing in the channel in the on state depends in particular on the polarization of the gate electrode.
• the multilayer structure comprises at least one pair of layers formed of a superconducting layer and a non-superconducting layer.
• the field effect produced by polarization of the gate electrode directly affects the carrier rate in the superconducting channel.
• the maximum current density of the channel is therefore strongly limited.
• the superconducting field effect transistor of the state of the art thus makes it possible to control only small currents.
• the invention therefore aims to enable the control of high currents, and to increase the current gain between the source electrode and the drain electrode, when the transistor is conducting.
• the subject of the invention is a transistor of the aforementioned type, characterized in that a layer of semiconductor material is disposed between the channel and the gate electrode, so as to allow control of the critical current of the superconducting channel by controlling the surface roughness of said channel, said surface roughness being controlled by combining the proximity effect between the superconducting channel and the layer of semiconductor material, and the field effect in the layer of semiconductor material by biasing the gate electrode, said critical current being controlled between a minimum value Icjnin by decreasing the surface roughness under the effect of an accumulation of free carriers of the semiconductor at the interface between the semiconductor layer and the channel for a first bias voltage of the gate electrode, and a maximum value Icjnax by increasing the surface roughness under the effect of free carrier depletion of the semiconductor at the interface between the semiconductor layer and the channel for a second bias voltage of the gate electrode.
• the transistor comprises one or more of the following characteristics, taken individually or according to all the technically possible combinations:
• the gate electrode is galvanically isolated from the channel by an insulating layer disposed on the layer of semiconductor material, and the transistor is a MOSFET transistor; the transistor is a JFET transistor;
• the substrate is a semiconductor substrate
• the substrate is an amorphous substrate of the glass or quartz type
• the substrate is a metal substrate
• the substrate is a flexible substrate of the polymer type;
• the superconducting channel is made of one of the group consisting of: niobium, aluminum, indium lead, niobium titanium, niobium tin and magnesium diboride;
• the critical current is determined by the width of the superconducting channel, and the maximum value Icjnax is greater than or equal to 50 A / cm,
• the critical current is determined by the width of the superconducting channel, and the minimum value Icjnin is between 0 A / cm and 0.5A / cm, the thickness of the superconducting channel is between 3 nm and 1 cm,
• the source and drain electrodes are of superconductive material
• the channel is a channel in fins.
• the invention also relates to a manufacturing method of the aforementioned type, characterized in that it comprises the addition of a layer of semiconductor material between the channel and the gate electrode, so as to allow a control the critical current of the superconducting channel by controlling the surface roughness of said channel, said surface roughness being controlled by combining the proximity effect between the superconducting channel and the semiconductor material layer and the field effect in the semiconductor material layer by polarization of the gate electrode, between a minimum value Icynin by reducing the surface roughness under the effect of an accumulation of free carriers of the semiconductor at the interface between the layer; semiconductor and the channel, and a maximum value Icjnax by increasing the surface roughness under the effect of a depletion of semiconductor free carriers at the interface between the semiconductor layer and channel.
• the manufacturing method comprises one or more of the following characteristics, taken separately or in any technically possible combination:
• the method comprises the addition of an insulating layer between the gate electrode and the layer of semiconductor material,
• the thickness of the superconducting channel is between 3 nm and 1 cm
• the method comprises producing the substrate made of a semiconductor material
• the process comprises producing the substrate in an amorphous material of the glass or quartz type
• the method comprises making the substrate of a metal or a metal alloy, the method comprises producing the substrate in a flexible material of the polymer type,
• the method comprises selecting the material of the superconducting channel from the group consisting of: niobium, aluminum, indium lead, niobium titanium, niobium tin and magnesium diboride,
• the method comprises forming the canal in the form of a channel in fins.
• FIG. 1 is a schematic representation of the superconducting field effect transistor according to a first embodiment of the invention
• FIG. 2 is an operating flow diagram of the manufacturing method according to the first embodiment of the invention.
• FIG. 3 is a schematic representation of the superconducting field effect transistor according to a second embodiment of the invention.
• FIG. 4 is an operating flow diagram of the manufacturing method according to the second embodiment of the invention.
• a field effect superconducting transistor 2 comprises a source electrode 4, a drain electrode 6 and a gate electrode 8.
• the gate electrode 8 is electrically isolated from the remainder of the transistor by a gate insulator layer 10.
• the source 4 and drain 6 electrodes are connected by a superconducting channel 12.
• the transistor 2 is of the Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET) type or metal-oxide gate field effect transistor.
• MOSFET Metal-Oxide Semiconductor Field-Effect Transistor
• a layer of semiconductor material 14 is disposed between the channel 12 and the insulating layer 10 of the gate electrode.
• the source electrode 4, the drain electrode 6 and the superconducting channel 12 are arranged on a substrate 16.
• the source 4, drain 6 and gate 8 electrodes are metallic.
• the gate electrode 8 is, for example, aluminum or tungsten.
• the source 4 and drain 6 electrodes are, for example, aluminum or tungsten.
• the insulating layer 10 is made of thermal oxide, for example silicon dioxide (SIO 2 ).
• the superconducting channel 12 extends between the source electrode 4 and the drain electrode 6 in a longitudinal direction.
• the channel 12 has a width L in a transverse direction, perpendicular to the longitudinal direction.
• the width L of the channel 12 is between 10 nanometers and 0.1 micrometer, preferably equal to 100 nanometers.
• the channel 12 is of thickness E, visible in FIG. 1, between 3 nanometers and one centimeter, preferably equal to 0.1 micrometer.
• the superconducting material of channel 12 is a type II superconducting material, such as niobium (Nb).
• the surface of the channel 12 in contact with the layer of semiconductor material 14 is called the upper surface of the superconducting channel 12, and the surface in contact with the substrate 16 is called the inner surface of the superconducting channel 12.
• the layer 14 of semiconductor material is adapted to allow a control of the critical current Ic of the superconducting channel 12 between a minimum value lc_min and a maximum value Icjnax by controlling the surface roughness of the channel 12.
• the surface roughness is controlled by combination of the effect of proximity between the superconducting channel 12 and the layer 14 of semiconductor material, and the field effect in the layer 14 of semiconductor material by polarization of the gate electrode 8.
• the critical current Ic is determined by the width L of the superconducting channel 12.
• the maximum value Icjnax of the critical current is greater than or equal to 50 amperes per centimeter.
• the minimum value Icjnin is between 0 Ampere per centimeter and 0.5 Ampere per centimeter, preferably equal to 0.1 ampere per centimeter.
• the substrate 16 made of a semiconductor material, such as solid silicon.
• a semiconductor material such as solid silicon.
• the manufacturing process begins in step 100 by producing the semiconductor substrate 16.
• the process continues in step 110 by forming the source 4 and drain 6 metal electrodes on the semiconductor substrate 16.
• the superconducting channel 12 is then produced in step 120 by depositing niobium between the source 4 and drain 6 electrodes, along the width L, until the thickness E is obtained.
• the process comprises, in step 130, the addition of the layer 14 of semiconductor material on the superconducting channel 12, so as to allow a control of the critical current Ic of the superconducting channel 12 by controlling the surface roughness of the channel 12 .
• the manufacturing process is continued in step 140 by the formation of the insulating layer 10 on the layer of semiconductor material 14.
• step 150 ends in step 150 by forming the tungsten gate electrode 8 on the insulating layer 10 of silicon dioxide.
• the operating principle of the superconducting transistor 2 lies in the control of the electrical resistance of the channel 12 under the action of the polarization of the gate electrode 8.
• the value of the electrical resistance of the channel 12 is substantially zero if the superconducting channel 12 is in a non-dissipative superconductive state, or a conducting state. If, on the contrary, the superconducting channel 12 is in a dissipative state, or a blocked state, then the electrical resistance of the channel is non-zero. This results in a switching behavior of the transistor 2 between the superconductive or non-dissipative state, and the dissipative state. This switching behavior does not exclude a linear mode in which the channel resistance varies in proportion under the biasing action of the gate electrode 8.
• the conduction of the channel 12 is controlled by the bias voltage V G s applied between the gate electrode 8 and the source electrode 4.
• the bias voltage V G applied between the gate electrode 8 and the source electrode 4 is called the bias voltage Vg of the gate electrode 8.
• the free carriers of the semiconductor material of the layer 14 accumulate at the interface between the layer of semiconductor material 14 and the channel 12 superconducting, which has the effect of reducing the surface roughness by proximity effect.
• the minimum value Icjnin of the critical current Ic is obtained for a minimum roughness of the upper surface of the superconducting channel 12.
• the free carriers of the semiconductor material of the layer 14 are depleted at the interface between the layer of semiconductor material 14 and the superconducting channel 12, which has the effect of increasing the surface roughness by proximity effect.
• the maximum value Icjnax of the critical current Ic is obtained for a maximum roughness e of the surface of the superconducting circuit.
• the surface roughness of the superconducting channel 12 contributes to vortex anchoring by providing sites for connecting non-normal vortices to the average surface.
• the vortex being anchored they do not disturb the superconducting regime of the channel 12, which still acts substantially as a perfect conductor, which corresponds to a strong critical current.
• the displacement of the vortex network is not constrained when the surface of the channel 12 is slightly rough, or even smooth.
• the movement of the vortex network then creates an electromotive force, since each vortex carries a magnetic flux, and the superconducting channel 12 no longer acts as a perfect conductor, which corresponds to a low critical current.
• a sample of high roughness has a high critical current
• a sample of low roughness has a low critical current.
• the critical current is substantially zero for a substantially smooth surface.
• the superconducting transistor 2 makes it possible to control the anchoring or the decanting of the vortices, and thus to control the threshold value for the appearance of a non-electrical resistance. null of the superconducting channel 12.
• the so-called proximity effect characterizes the fact that a layer of highly doped semiconductor material deposited on a superconducting layer itself becomes superconductive on a film whose thickness is related to the mobility and to the concentration of free carriers.
• the bias voltage Vg of the gate electrode 8 leads to increasing the concentration of free carriers in the vicinity of the interface between the superconducting channel 12 and the semiconductor layer 14, then the roughness is smoothed and decreases, and the critical current Ic decreases to the minimum value Icjnin. When the value of the critical current Ic is close to the minimum value Icjnin, the superconducting transistor 2 is in the off state. If, on the other hand, the bias voltage Vg of the gate electrode 8 leads to depleting the interface between the superconducting channel 12 and the semiconductor layer 14, then the surface roughness increases, implying an increase in the critical current Ic up to at its maximum value Icjnax. When the value of the critical current Ic is close to the maximum value lc_max, the superconducting transistor 2 is in the on state.
• the interface between the semiconductor layer 14 and the superconducting channel 12 thus behaves as a surface with variable roughness as a function of the bias voltage Vg of the gate electrode 8.
• the transistor 2 When the superconducting transistor 2 is conducting, the current flows from the source electrode 4 to the drain electrode 6 in both the superconducting channel 12 and in the thickness of the semiconductor material layer 14 where the carriers are located. free. This thickness of layer 14 of semiconductor material is then superconducting by proximity effect.
• the transistor 2 according to the invention thus allows the direct control, by electrostatic field effect, of the critical current Ic of the superconducting channel 12.
• the superconducting transistor 2 according to the invention is capable of being used for applications in the field of high currents, such as power switching and current limiting.
• the dissipative state of the superconducting channel 12 does not result from a reduction of the carrier rate, but from the decrease of the critical current Ic by vortex decanting.
• the superconducting transistor 2 makes it possible to control a current of intensity greater than or equal to 50 amperes for each centimeter of the width L of the superconducting channel 12.
• the current gain of the transistor 2 is important.
• the superconducting transistor 2 according to the invention is capable of being used for applications in the field of low currents.
• the frequency response of the superconducting transistor 2 according to the invention is high, since the transition between the dissipative state of the channel 12 and the superconductive or non-dissipative state is due to the dynamics of the vortices.
• the manufacturing method according to the invention of the superconducting transistor 2 does not require a heavy technological means making it possible to deposit or etch at the nanoscale.
• the manufacturing method according to the invention does not require a superconducting channel of very small thickness.
• the layer undergoing the field effect due to the polarization of the gate electrode 8 is not the superconducting channel 12 itself, but only the semiconductor layer 14 deposited on the channel 12.
• FIG. 3 and 4 illustrate a second embodiment of the invention, for which the elements similar to the embodiment described above are identified by identical references.
• the superconducting field effect transistor 2 does not comprise an insulating layer between the gate electrode 8 and the layer of semiconductor material 14, as represented in FIG.
• the transistor 2 is of JFET (Junction Field Effect Transistor) type or junction field effect transistor, for which the gate electrode 8 is directly in contact with the channel 12.
• the method of manufacturing transistor 2 according to the second embodiment does not include a step of forming an insulating layer on the layer of semiconductor material 14.
• Step 155 the last step of the manufacturing process, consists of the formation of the gate electrode 8, directly on the layer of semiconductor material 14.
• the operation of this second embodiment is identical to that of the first embodiment. and is therefore not described again.
• the substrate 16 is an amorphous substrate, of the glass or quartz type.
• the substrate 16 is a metal substrate.
• the substrate 16 is a flexible substrate, of polymer type.
• the source 4 and drain 6 electrodes are made of a superconducting material.
• the source 4 and drain 6 electrodes are made of a doped semiconductor material.
• the superconducting channel 12 is a finned channel.
• the superconducting material of the channel 12 is aluminum (Al), indium lead (PbIn), niobium titanium (NbTi), niobium tin (NbSn), or magnesium diboride ( MgB 2 ).
• the superconducting transistor according to the invention makes it possible to control the passage of currents of high intensity through its superconducting channel, since the density of the free carriers in the superconducting channel is not affected by the field effect which acts only on the layer of semiconductor material. It is also conceivable that the superconductive transistor according to the invention makes it possible to amplify the current in the channel with a large gain, due to the large variation in the resistance of the channel under the field effect, due to the polarization of the electrode grid.

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• 2008
  • 2008-06-02 FR FR0853620A patent/FR2932012B1/fr not_active Expired - Fee Related
• 2009
  • 2009-05-29 WO PCT/FR2009/051010 patent/WO2009156657A1/fr not_active Ceased
  • 2009-05-29 US US12/995,781 patent/US20110254053A1/en not_active Abandoned
  • 2009-05-29 EP EP09769498A patent/EP2294637A1/de not_active Withdrawn

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