Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
  • H10P90/19—Preparing inhomogeneous wafers
  • H10P90/1904—Preparing vertically inhomogeneous wafers
  • H10P90/1906—Preparing SOI wafers
  • H10P90/1914—Preparing SOI wafers using bonding
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N30/00—Piezoelectric or electrostrictive devices
  • H10N30/01—Manufacture or treatment
  • H10N30/07—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base
  • H10N30/072—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies
  • H10N30/073—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
  • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
  • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
  • H10P14/6326—Deposition processes
  • H10P14/6328—Deposition from the gas or vapour phase
  • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
  • H10P14/6336—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
  • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
  • H10P14/66—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
  • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
  • H10P14/66—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
  • H10P14/668—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials
  • H10P14/6681—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si
  • H10P14/6682—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
  • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
  • H10P14/69—Inorganic materials
  • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
  • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
  • H10P14/6922—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
  • H10P14/6927—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
  • H10W10/10—Isolation regions comprising dielectric materials
  • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Definitions

• the invention relates to a support having a layer for trapping electrical charges, the support being intended to receive a thin crystalline layer by a layer transfer technique.
• a composite substrate formed from such a support finds its application in the field of integrated electronic components, in particular radio frequency (RF) components processing signals whose frequency can typically be between 20 kHz and 300 GHz, or more.
• the thin layer of the composite substrate may consist of a semiconductor material such as silicon or an insulating material, such as a material having piezoelectric and/or ferroelectric properties.
• the invention also relates to the composite substrate comprising this support and onto which the thin layer has been transferred.
• the invention also relates to the method of manufacturing the support and the method of manufacturing the composite substrate incorporating such a support.
• documents US7585748 and US9293473 propose to form the electrical charge trapping layer (and more concisely designated “trapping layer” in the remainder of this description) in the form of 'a layer of polycrystalline silicon arranged on a silicon base substrate.
• the trapping layer can be formed more generally from a non-monocrystalline layer having structural defects, such as dislocations, grain boundaries, amorphous zones, interstices, inclusions, pores, etc., these structural defects being capable of trapping electrical charges.
• the trapping layer can thus be formed by implantation of a relatively heavy species, such as argon, in a superficial thickness of the base substrate, in order to form the structural defects constituting the electrical traps.
• a relatively heavy species such as argon
• document US10224233 proposes a trapping layer formed of nanocavities arranged in a superficial zone of a base substrate, these nanocavities being obtained by implantation of helium and nitrogen.
• Document US2015115480 proposes to form the trapping layer as a stack of passivated elementary amorphous or polycrystalline layers. These elementary layers may in particular be composed of silicon, germanium, silicon germanium. Through this stacking, we seek to make the trapping layer more robust to the heat treatments that the support is required to undergo, in particular during the stages of manufacturing the composite substrate using such a support.
• the trapping layer is an amorphous layer of silicon doped with carbon. This layer is formed on a silicon base substrate having a surface layer of silicon oxide.
• Document US10468295 provides for forming a layer of silicon nitride or silicon oxynitride between a trapping layer of polycrystalline silicon and a dielectric layer of silicon oxide. This layer can be obtained by deposition or by nitriding/oxynitriding of the trapping layer and aims to preserve the resistivity of the trapping layer and to avoid its recrystallization.
• this state of the art reveals the need to have a support for a composite substrate comprising a trapping layer which has a high resistivity and is stable in temperature.
• This temperature stability is an important characteristic, because the manufacture of a composite substrate comprising such a support implements heat treatments typically raising the temperature of the support to more than 1000°C, which tends to cause the desired characteristics of the support by recrystallization of the layer and disappearance of structural defects in this layer.
• the RF performance of a component can be estimated by carrying out an RF characterization of the composite substrate (and more particularly of the support of this composite substrate) on or in which the component is intended to be formed.
• the RF performance of a substrate can be characterized by an HD2 second harmonic distortion measurement.
• a support comprising a trapping layer making it possible to form a support having high RF performance which is stable with temperature, these performances being established by the HD2 measurement.
• a high trap density also makes the RF performance of the substrate less sensitive to the diffusion of species in the trapping layer which tends to electrically passivate the traps. This may, for example, involve the diffusion of hydrogen or lithium (particularly when the thin layer of the composite substrate is formed of a piezoelectric material based on lithium).
• the object of the invention proposes a support for a composite substrate, the support comprising an interlayer layer disposed on a base substrate, the interlayer layer comprising a trapping layer in contact with the substrate base formed from a silicon-rich oxide consisting of silicon in an atomic concentration of silicon between 70% and 90% and of oxygen in an atomic concentration between 10% and 30%.
• the object of the invention proposes a composite substrate comprising a thin monocrystalline layer placed on a support as proposed previously.
• the single-crystalline thin layer can be made of silicon or a piezoelectric material
• Figures 3a, 3b, 3c represent a trapping layer according to the invention in various crystal forms
• Figures 4a, 4b represent graphs of the silicon atomic concentration profile in an interlayer of a support according to the invention
• the support 1 comprises an interlayer 3 arranged on a base substrate 2.
• the interlayer 3 comprises a trapping layer 3a in contact with the base substrate 2.
• the interlayer layer can also comprise, as this is shown on the , a dielectric layer 3b arranged on and in contact with the trapping layer 3a, but this dielectric layer 3b is perfectly optional. Note that it is not imperative that the interlayer 3 present, in such a case, an abrupt interface between the trapping layer 3a and the dielectric layer 3b.
• This interlayer 3 can thus present, in its thickness, a progressive transition in its constitution leading to defining the trapping layer 3a and the dielectric layer 3b. This aspect of the invention will be illustrated in a later section of the present description.
• the interlayer 3 consists entirely of the trapping layer 3a.
• the support 1 can be in the form of a circular plate whose diameter can be 100, 150, 200, 300 or even 450mm.
• the base substrate 2 of the support 1 on which the interlayer 3 rests typically has a thickness of several hundred micrometers.
• the base substrate 2 has a high resistivity, greater than 1000 ohms centimeters, and more preferably still, greater than 2000 ohms centimeters. This limits the density of the charges, holes or electrons, which are likely to move in the base substrate 2.
• the invention is not limited to a base substrate 2 having such resistivity, and it provides also RF performance advantages when the base substrate 2 has a more consistent resistivity, of the order of a few hundred ohms centimeters, for example less than 1000 ohm.cm, or 500 ohm.cm or even 10 ohm .cm.
• an amorphous layer made of silicon dioxide for example, directly interposed between the base substrate 2 and the trapping layer 3a.
• this amorphous layer can be a layer of native oxide present on the surface of this substrate or formed intentionally by chemical or thermal oxidation of the base substrate.
• the trapping layer 3a conforming to the description which follows is particularly stable with temperature, and the presence of the amorphous layer is perfectly optional.
• the trapping layer 3a is a silicon-rich oxide layer.
• This silicon-rich oxide layer is made up of silicon, oxygen and, optionally, nitrogen.
• atomic concentration of silicon in the layer is between 40% or 50% and 99.9%. Oxygen and, possibly, nitrogen are present in substoichiometric atomic concentrations.
• Such a layer has the particular advantage of having a particularly high density of defects, forming traps for electrical charges. It is therefore likely to have a very high resistivity, up to approximately 10 ⁇ 12 ohm.cm. More generally, this resistivity is between 10 ⁇ 5 ohm.cm and 10 ⁇ 12 ohms.cm.
• a dielectric layer of silicon oxide (stoichiometric) has a resistivity of the order of 10 ⁇ 15 ohm.cm and a trapping layer of the state of the art, made of polycrystalline silicon, has a typical resistivity of the order of 10 ⁇ 4 ohm.cm.
• the composition of the trapping layer can be determined by secondary ion mass spectrometry (“SIMS” measurements for “Secondary Ion Mass Spectrometry”).
• SIMS secondary ion mass spectrometry
• XPS X-ray photoelectron spectroscopy
• ion beam etching ion beam etching
• the atomic concentrations of silicon, oxygen and, possibly, nitrogen be constant in the thickness of the trapping layer 3a. In certain implementation modes, this concentration can vary, while remaining within the concentration limits giving this layer the quality of being rich in silicon. In certain other modes of implementation, these atomic concentrations are chosen to be constant.
• the silicon-rich trapping layer is not intentionally doped. It does not include any species other than silicon, oxygen and, possibly, nitrogen. If other species are incorporated into the layer, they are in proportions not exceeding simple traces, less than 0.1%.
• a silicon-rich layer is formed from an amorphous matrix.
• This amorphous matrix may comprise crystalline silicon inclusions or crystalline silicon grains, the density and size of these inclusions and/or these grains in the amorphous matrix being dependent on the relative proportions of oxygen, nitrogen and silicon. in the layer and the heat treatments that it received.
• a layer rich in silicon can be entirely amorphous or entirely polycrystalline, the amorphous matrix then being in the latter case reduced to amorphous inclusions present between the grains of the polycrystal.
• the polycrystalline layer is formed of silicon grains g whose size distribution has a peak (which defines the average grain size) close to 100 nm or less than 100 nm. This average size is much smaller than the average grain size of a conventional trapping layer, in polycrystalline silicon (of the order of 300nm).
• the atomic concentration of silicon in a silicon-rich layer is lower, for example in the range extending from 40% to 90% or extending from 50% to 90%, and it includes an oxygen concentration and, possibly in nitrogen, greater than or equal to 10%, this takes a mainly amorphous form. It is then composed of elements of nanometric dimensions of Si, SiO, SiON, SiN which gives it this amorphous nature, as is illustrated in the .
• a silicon-rich layer can take the form of an amorphous matrix, in which crystalline silicon inclusions are embedded. These IC inclusions can have a size less than 10 nm, and sometimes even less than 5 nm.
• the amorphous, polycrystalline or intermediate form can be affected by the heat treatments applied to this layer during or after its manufacture, or even during use of the support.
• the oxygen, nitrogen and/or silicon concentration limits are given for illustration purposes only. The person skilled in the art will be able to adjust, using a series of experiments that are very simple to carry out, these concentrations making it possible to arrive at a trapping layer 3a having the desired structural characteristics.
• the exact crystalline nature of the layer can in particular be observed by microscopy, for example by transmission electron microscopy (TEM) or by Raman measurement.
• a support 1 in accordance with the invention has a lower resistivity characteristic measured by the HD2 technique (presented in the introduction). -80dB. Some products have greater requirements. Thus, we expect that a support 1 of a composite substrate of silicon on insulator (formed of a layer of monocrystalline silicon transferred onto the support) has a resistivity characteristic HD2 lower than -80 dB after exposure to a thermal budget of 1100 °C for 2 hours.
• the trapping layer 3a has a thickness which can be between 10 nm and 30 micrometers, and typically between 20 nm and 5 micrometers. Preferably, this thickness is greater than 50nm or 100nm so that the quantity of traps is sufficient. Preferably, this thickness is less than 2 micrometers, or even 1 micrometer, to limit the quantity of material, and the possible constraints that this layer can apply to the support 1, and which could deform it. But this advantageous range of thickness is in no way limiting, and we can choose to form a trapping layer 3a of any suitable thickness, depending on the needs of the intended application.
• the trapping layer 3a has a first surface in contact with the base substrate 2. It has a second surface opposite the first surface.
• the second surface of the trapping layer 3 has a low roughness so that it is not necessary to treat it to improve its surface condition. This roughness can be less than 0.6 nm in root mean square value measured over a field of 10 micrometers by 10 micrometers.
• the interlayer 3 can comprise, in addition to the trapping layer 3a which has just been described, a dielectric layer 3b, placed on and in contact with the trapping layer.
• dielectric layer we mean a layer having a resistivity of the order of 10 ⁇ 10 ohm.cm and more.
• the resistivity of the dielectric layer 3b is, in all cases, greater than the resistivity of the trapping layer 3a.
• This dielectric layer 3b can, generally speaking, be of any type and of suitable thickness. But advantageously, a support 1 conforming to the present description has a dielectric layer 3b composed of silicon, oxygen and/or nitrogen, that is to say the same elements as those which can compose the trapping layer 3a. This characteristic makes it possible to form the interlayer 3 in a single step, by successively forming the trapping layer 3a and the dielectric layer 3b, "in-situ", for example in the same deposition equipment.
• the dielectric layer 3b has a thickness typically between 10 nm and 10 micrometers, essentially dictated by the need for the application of the composite substrate S that the support 1 is intended to form.
• the exposed face of this layer can benefit from the low roughness property previously presented for the trapping layer 3a.
• This interlayer 3 can thus have a free surface of less than 0.6 nm in root mean square value measured over a field of 10 micrometers by 10 micrometers.
• the dielectric layer 3b consists at least partly of silicon oxide or silicon nitride, in particular in a superficial part.
• a support 1 having an exposed surface whose nature, silicon oxide or nitride, is perfectly known. This surface can in particular be prepared, by polishing, cleaning, activation, according to controlled processes, to transfer a thin layer using layer transfer technology, and thus form a composite substrate.
• this transfer is usually carried out by assembling a free face of a donor substrate to the support substrate 1, preferably by molecular adhesion.
• This assembly is generally facilitated by the presence of an amorphous layer, for example of silicon dioxide or silicon nitride on at least one of the faces to be assembled.
• an amorphous layer for example of silicon dioxide or silicon nitride
• the interlayer 3 of the support superficially presents such an amorphous surface layer (which can be the trapping layer 3a or the dielectric layer 3b)
• the donor substrate itself it is not necessary for the donor substrate itself to be provided with it.
• the donor substrate is not excluded, and it is sometimes possible for the donor substrate to be provided with a thin amorphous thickness (for example a layer of silicon dioxide having a thickness less than 150nm).
• the donor substrate has finished or semi-finished components, the transfer aiming to place these components on the support 1 to take advantage of its radio frequency properties.
• the donor substrate is devoid of any components in order to transfer a thin layer 4 consisting of a material of crystalline nature, and advantageously monocrystalline.
• the donor substrate can take the form of a circular plate, the dimension of which can correspond to that of the support.
• the donor substrate is reduced in thickness to form thin layer 4.
• This reduction step can be carried out by mechanical thinning. or chemical.
• the reduction in thickness of the donor substrate can preferably be carried out by fracture at the level of a weakening plane previously introduced into the donor substrate, for example by implantation of light species such as hydrogen and/or helium. This weakening plane defines, with the free surface of the donor substrate, the thin layer 4.
• finishing steps of the thin layer 4 can be applied, such as a polishing step, heat treatment under a reducing or neutral atmosphere, sacrificial oxidation, etc.
• the finishing steps include exposing the composite substrate to relatively high temperatures, above 600°C, for a period of at least one hour.
• the thin layer 4 added is made of silicon
• the composite structure S is exposed to a thermal budget of at least 1000°C for 1 hour.
• the thin layer 4 added is made of a piezoelectric material
• the composite structure S is exposed to a thermal budget of at least 600°C for 1 hour.
• the trapping layer 3a being temperature stable, the RF properties of the composite substrate S are not excessively altered by the heat treatments applied to it during the finishing stages.
• the thin layer 4 is a thin monocrystalline piezoelectric layer transferred directly onto the trapping layer 3a.
• the support does not have a dielectric layer 3a.
• the single-crystal piezoelectric thin layer may be lithium tantalate or lithium niobate.
• Such a composite substrate is particularly suitable for receiving surface wave acoustic devices.
• the trapping layer 3a by its nature, has acoustic characteristics close to a layer of silicon dioxide usually used in these devices. In such a case, the trapping layer then has the dual function of improving the radio frequency characteristics of the component and adequately propagating the acoustic waves.
• the interlayer 3 has a dielectric layer 3b made of silicon dioxide, the thickness of which can be between 10 nm and 10 micrometers.
• Thin layer 4 is a layer of monocrystalline silicon.
• the composite substrate S then forms a silicon-on-insulator substrate.
• the base substrate 2 is provided which is placed in a chamber of conventional deposition equipment.
• the base substrate 2 can be prepared, for example to remove a native oxide layer from its surface. This step is not obligatory and this oxide can be preserved.
• a sequence of formation of the interlayer 3 therefore comprises a step of deposition, directly on the base substrate 2 provided or not with its amorphous layer, of a trapping layer 3a of silicon-rich oxide, according to one of the preferred implementation modes presented previously.
• the deposition step comprises the introduction, into the deposition chamber, of a first silicon precursor gas (for example silane, of formula SiH4) and at least one second oxygen precursor gas (nitrous oxide or dioxygen), and possibly nitrogen (for example nitrous oxide of formula N2O).
• a first silicon precursor gas for example silane, of formula SiH4
• at least one second oxygen precursor gas nitrous oxide or dioxygen
• nitrogen for example nitrous oxide of formula N2O
• a carrier gas for example nitrogen, argon or helium.
• the precursor gases react in the deposition chamber, under controlled pressure and temperature conditions, to gradually form the trapping layer 3a.
• the deposition When the deposition is carried out using the PECVD technique, it is carried out at a moderate temperature, typically between 150°C and 600°C, and at a subatmospheric pressure for example of a few Torr (i.e. a few hundred Pascal).
• a moderate temperature typically between 150°C and 600°C
• a subatmospheric pressure for example of a few Torr (i.e. a few hundred Pascal).
• LPCVD When it is carried out using the LPCVD technique, it is carried out at a temperature typically between 550°C and 750°C, also at a subatmospheric pressure of for example a few Torr (i.e. a few hundred Pascal).
• the invention is of course in no way limited to a particular deposition technique or to particular precursor gases.
• APCVD atmospheric Pressure Chemical Vapor Deposition
• HDP CVD high Density Plasma Chemical Vapor Deposition
• a relatively low temperature between 100°C and 450°C, and at a pressure of around 10 mTorr (i.e. around 1.33 Pascal).
• SACVD Sub-Atmospheric Chemical Vapor Deposition
• chemical vapor deposition at sub-atmospheric pressure we can also use an epitaxy frame to form this layer using a generic vapor deposition technique.
• the sequence of formation of the interlayer 3 is controlled to vary the atomic concentration of silicon continuously or suddenly.
• the atomic concentration of silicon can be chosen to decrease continuously in the thickness of the interlayer 3 moving away from the base substrate 2.
• the atomic concentration of one of these species increasing to form a dielectric layer 3b, for example carbon dioxide silicon or silicon nitride comprising a stoichiometric silicon atomic concentration, on the trapping layer 3a.
• the dielectric layer 3b advantageously comprises a surface thickness of silicon dioxide or silicon nitride.
• Example 1 Silicon-rich trapping layer consisting of silicon, oxygen and nitrogen.
• the base substrates of the supports all had a high resistivity (3 kohm.cm).
• the trapping layers were formed using a PECVD technique.
• a first silicon precursor gas consisting of silane (SiH4) and a second precursor gas of oxygen and nitrogen consisting of nitrous oxide (N2O). These precursor gases were supplemented by a nitrogen carrier gas.
• the deposition chamber was maintained at a pressure of 3 Torr (i.e. 400 Pascal), and the plasma (at 13.55MHz) had a power of 300W.
• the flows were maintained to form a trapping layer of chosen thickness of 200nm or 1 micrometer for media types 1 and 2, and between 70 nm and 500 nm for media type 3.
• the support is prepared by polishing to form a chamfer making the different layers making up the support accessible, in their depth.
• the ends of two electrodes spaced a fixed distance apart and forming a segment parallel to the edge of the chamfer are then applied to the chamfered part of the substrate.
• a determined voltage is applied between the two electrodes, the resistance between them is measured, then the electrical resistivity of the support at the measurement depth is deduced from this measurement.
• the support subjected to the SRP measurement consisted of a high resistivity base substrate (3.5 kohm.cm), and a trapping layer obtained by a PECVD technique by controlling the nitrous oxide/silane ratio to 0 ,15.
• the trapping layer was atomically composed of 76.5% silicon, 8.5% oxygen, and 15% nitrogen.
• the trapping layer has a thickness of 1 micrometer.
• the resistivity measurement is reported by the TR trace on this .
• we have drawn the line TR' which corresponds to the maximum resistivity of a conventional trapping layer consisting of a thickness of 2 micrometers of polycrystalline silicon.
• SRP characterization measures the electrical performance of the trapping layer as such, but does not allow the RF performance of the support to be fully anticipated. This performance is in fact also affected by other parameters than that linked to the resistance characteristic of the trapping layer, for example its thickness or the resistivity characteristics of the base substrate.
• the HD2 measurement presented in the introduction to this application, makes it possible to evaluate more generally the RF performance of a support when it is used as a support for a composite substrate receiving RF components.
• type 3 supports were used to produce composite substrates comprising a thin layer 4 made of a monocrystalline piezoelectric material (lithium tantalate ) in accordance with the layer transfer process described above.
• a silicon oxide dielectric layer (designated “BOX” in the table below) is disposed between the trapping layer (designated “TR” in this table) and the thin piezoelectric layer.
• the trapping layer was exposed to a maximum temperature of 850°C for 2 h.
• Example 2 Silicon-rich trapping layer consisting of silicon and oxygen.
• the RF performance measurements (average) measured by the HD2 technique (15dBm input signal, at 900MHz), as a function of the silicon concentration are as follows:
• the HQF measurement (theoretical value of HD2 for a “perfect” trapping layer) is expected to be -88dB.
• Type 4 media exhibited the same level of RF performance as measured by HD2 regardless of trapping layer thickness. This thickness therefore does not seem to affect this performance.
• it is made up of silicon in an atomic concentration of between 70% and 90% and of oxygen in an atomic concentration of between 10% and 30%.

Landscapes

• Engineering & Computer Science (AREA)
• Manufacturing & Machinery (AREA)
• Formation Of Insulating Films (AREA)

Applications Claiming Priority (2)

Publications (1)

Family

ID=85222155

Family Applications (1)

Country Status (4)

Families Citing this family (4)

Family Cites Families (16)

• 2023
  • 2023-11-27 EP EP23812956.3A patent/EP4627620A1/de active Pending
  • 2023-11-27 WO PCT/EP2023/083212 patent/WO2024115410A1/fr not_active Ceased
  • 2023-11-27 JP JP2025555931A patent/JP2026511205A/ja active Pending
  • 2023-11-28 TW TW112146093A patent/TW202449852A/zh unknown

Also Published As

Similar Documents

Legal Events