ES2015149A6 - Electronic circuit for loading and testing regular trees for data processing - Google Patents

Electronic circuit for loading and testing regular trees for data processing

Info

Publication number
ES2015149A6
ES2015149A6 ES8901708A ES8901708A ES2015149A6 ES 2015149 A6 ES2015149 A6 ES 2015149A6 ES 8901708 A ES8901708 A ES 8901708A ES 8901708 A ES8901708 A ES 8901708A ES 2015149 A6 ES2015149 A6 ES 2015149A6
Authority
ES
Spain
Prior art keywords
loading
testing
trees
data processing
regular
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES8901708A
Other languages
Spanish (es)
Inventor
Montero Ricardo Ramos
Garcia Carlos Perello
Garcia Luis Paris
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to ES8901708A priority Critical patent/ES2015149A6/en
Publication of ES2015149A6 publication Critical patent/ES2015149A6/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Tests Of Electronic Circuits (AREA)

Abstract

Electronic circuit for loading and testing regular trees for data processing. The circuit is applicable to the assembly of apparatuses for data processing, display of images and for the search for data in databases supported by computing installations. The circuit carries out two primordial functions, being the loading of the regular trees in the form of hierarchical structures of data comprising trees of the order r in a memory matrix, and the testing of the nodes of the regular tree to determine whether they are homogeneous or not. The circuit comprises a series of subassemblies logically related by bus lines, employing memory matrices and records of given capacities expressed in numbers of bits, the loading of a regular tree being effected in three phases, and the testing of the tree itself in five different phases.
ES8901708A 1989-05-19 1989-05-19 Electronic circuit for loading and testing regular trees for data processing Expired - Lifetime ES2015149A6 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
ES8901708A ES2015149A6 (en) 1989-05-19 1989-05-19 Electronic circuit for loading and testing regular trees for data processing

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
ES8901708A ES2015149A6 (en) 1989-05-19 1989-05-19 Electronic circuit for loading and testing regular trees for data processing

Publications (1)

Publication Number Publication Date
ES2015149A6 true ES2015149A6 (en) 1990-08-01

Family

ID=8262023

Family Applications (1)

Application Number Title Priority Date Filing Date
ES8901708A Expired - Lifetime ES2015149A6 (en) 1989-05-19 1989-05-19 Electronic circuit for loading and testing regular trees for data processing

Country Status (1)

Country Link
ES (1) ES2015149A6 (en)

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Date Code Title Description
FD1A Patent lapsed

Effective date: 20000301