ES2042382A2 - Estructura de test para la medida del desalineamiento entre niveles en tecnologias microelectronicas, basada en transistores mos con puerta triangular. - Google Patents

Estructura de test para la medida del desalineamiento entre niveles en tecnologias microelectronicas, basada en transistores mos con puerta triangular.

Info

Publication number
ES2042382A2
ES2042382A2 ES919102409A ES9102409A ES2042382A2 ES 2042382 A2 ES2042382 A2 ES 2042382A2 ES 919102409 A ES919102409 A ES 919102409A ES 9102409 A ES9102409 A ES 9102409A ES 2042382 A2 ES2042382 A2 ES 2042382A2
Authority
ES
Spain
Prior art keywords
misalignment
levels
mos transistors
measuring
test structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
ES919102409A
Other languages
English (en)
Other versions
ES2042382R (es
ES2042382B1 (es
Inventor
M Lozano
C Cane
C Perello
E Lora-Tamayo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Consejo Superior de Investigaciones Cientificas CSIC
Original Assignee
Consejo Superior de Investigaciones Cientificas CSIC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Consejo Superior de Investigaciones Cientificas CSIC filed Critical Consejo Superior de Investigaciones Cientificas CSIC
Priority to ES09102409A priority Critical patent/ES2042382B1/es
Publication of ES2042382A2 publication Critical patent/ES2042382A2/es
Publication of ES2042382R publication Critical patent/ES2042382R/es
Application granted granted Critical
Publication of ES2042382B1 publication Critical patent/ES2042382B1/es
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

LA ESTRUCTURA DE TEST PARA LA MEDIDA DEL DESALINEAMIENTO ENTRE NIVELES DE TECNOLOGIAS MICROELECTRICAS, BASADA EN TRANSISTORES MOS CON PUERTA TRIANGULAR, ES UN DISPOSITIVO MICROELECTRONICO COMPUESTO DE CUATRO TRANSISTORES MOS CON LA PUERTA TRIANGULAR, DISPUESTOS FORMANDO 90 ENTRE SI, CON LOS TERMINALES DE FUENTE UNIDOS, SENSIBLE AL DESALINEAMIENTO ENTRE LOS NIVELES DE PUERTA Y AREAS ACTIVAS EN TECNOLOGIAS AUTOALINEADAS. EL DESALINEAMIENTO SE OBTIENE A PARTIR DE LA MEDIDA DE LA CORRIENTE DE CANAL EN CADA UNO DE LOS TRANSISTORES, POLARIZANDO LOS MISMOS EN LA ZONA LINEAL O EN LA DE SATURACION.
ES09102409A 1991-10-30 1991-10-30 Estructura de test para la medida del desalineamiento entre niveles en tecnologias microelectronicas, basada en transistores mos con puerta triangular Expired - Fee Related ES2042382B1 (es)

Priority Applications (1)

Application Number Priority Date Filing Date Title
ES09102409A ES2042382B1 (es) 1991-10-30 1991-10-30 Estructura de test para la medida del desalineamiento entre niveles en tecnologias microelectronicas, basada en transistores mos con puerta triangular

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
ES09102409A ES2042382B1 (es) 1991-10-30 1991-10-30 Estructura de test para la medida del desalineamiento entre niveles en tecnologias microelectronicas, basada en transistores mos con puerta triangular

Publications (3)

Publication Number Publication Date
ES2042382A2 true ES2042382A2 (es) 1993-12-01
ES2042382R ES2042382R (es) 1995-08-16
ES2042382B1 ES2042382B1 (es) 1996-04-01

Family

ID=8274001

Family Applications (1)

Application Number Title Priority Date Filing Date
ES09102409A Expired - Fee Related ES2042382B1 (es) 1991-10-30 1991-10-30 Estructura de test para la medida del desalineamiento entre niveles en tecnologias microelectronicas, basada en transistores mos con puerta triangular

Country Status (1)

Country Link
ES (1) ES2042382B1 (es)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4386459A (en) * 1980-07-11 1983-06-07 Bell Telephone Laboratories, Incorporated Electrical measurement of level-to-level misalignment in integrated circuits
EP0080619A2 (en) * 1981-11-30 1983-06-08 International Business Machines Corporation Method for determining photomask alignment
US4647850A (en) * 1984-10-05 1987-03-03 Burroughs Corporation Integrated circuit for measuring mask misalignment
EP0370834A2 (en) * 1988-11-25 1990-05-30 Nec Corporation Semiconductor device, and method of manufacture

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4386459A (en) * 1980-07-11 1983-06-07 Bell Telephone Laboratories, Incorporated Electrical measurement of level-to-level misalignment in integrated circuits
EP0080619A2 (en) * 1981-11-30 1983-06-08 International Business Machines Corporation Method for determining photomask alignment
US4647850A (en) * 1984-10-05 1987-03-03 Burroughs Corporation Integrated circuit for measuring mask misalignment
EP0370834A2 (en) * 1988-11-25 1990-05-30 Nec Corporation Semiconductor device, and method of manufacture

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
BASE DE DATOS WPIL en QUESTEL. Semana 7906. Londres: Derwent Publications Ltd. AN 79-B2303B. Class U12 RH6 SU-A1-598159 (UFA AVIATION INST), resumen *

Also Published As

Publication number Publication date
ES2042382R (es) 1995-08-16
ES2042382B1 (es) 1996-04-01

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Legal Events

Date Code Title Description
FD1A Patent lapsed

Effective date: 20020425