ES2046984T3 - Metodo de fabricar un dispositivo semiconductor con tension de encapsulacion reducida. - Google Patents

Metodo de fabricar un dispositivo semiconductor con tension de encapsulacion reducida.

Info

Publication number
ES2046984T3
ES2046984T3 ES87202505T ES87202505T ES2046984T3 ES 2046984 T3 ES2046984 T3 ES 2046984T3 ES 87202505 T ES87202505 T ES 87202505T ES 87202505 T ES87202505 T ES 87202505T ES 2046984 T3 ES2046984 T3 ES 2046984T3
Authority
ES
Spain
Prior art keywords
voltage
manufacturing
semiconductor device
revestient
union
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES87202505T
Other languages
English (en)
Inventor
Myron Ralph Cagan
Douglas Frederick Ridley
Daniel James Belton
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Gloeilampenfabrieken NV filed Critical Philips Gloeilampenfabrieken NV
Application granted granted Critical
Publication of ES2046984T3 publication Critical patent/ES2046984T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/121—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/981—Auxiliary members, e.g. spacers
    • H10W72/983—Reinforcing structures, e.g. collars
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Die Bonding (AREA)

Abstract

UN DISPOSITIVO SEMICONDUCTOR CONTIENE UNA CAPA DE DESAHOGO DE TENSION (46) QUE TIENE UNA TEMPERATURA DE TRANSICION DE CRISTAL POR DEBAJO DE LOS 150 (GRADOS) C. LA CAPA GENERALMENTE DESCANSA SOBRE UN SISTEMA DE INTERCONEXION ELECTRICA (12) EN EL DISPOSITIVO PERO NO SE APOYA EN LAS AREAS DE RELLENO DE LA UNION. ESTO ALIVIA SUBSTANCIALMENTE LA TENSION TERMICAMENTE INDUCIDA QUE DE OTRA MANERA PODRIA DAÑAR LOS COMPONENTES ELECTRONICOS EN EL DISPOSITIVO MIENTRAS SIMULTANEAMENTE PERMITE EL MAXIMO DE TENSION EN LOS CONDUCTORES ELECTRICOS (32 Y 34) QUE SOBRESALEN DEL REVESTIMIENTO DE EMPAQUETADO EXTERNO (48) PARA PRODUCIRSE EN LAS AREAS DE UNION QUE PUEDAN TOLERAR LA TENSION. LA CAPA SE HACE PREFERIBLEMENTE MEDIANTE DISEÑO LITOGRAFICO.
ES87202505T 1986-12-19 1987-12-14 Metodo de fabricar un dispositivo semiconductor con tension de encapsulacion reducida. Expired - Lifetime ES2046984T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US94426886A 1986-12-19 1986-12-19

Publications (1)

Publication Number Publication Date
ES2046984T3 true ES2046984T3 (es) 1994-02-16

Family

ID=25481096

Family Applications (1)

Application Number Title Priority Date Filing Date
ES87202505T Expired - Lifetime ES2046984T3 (es) 1986-12-19 1987-12-14 Metodo de fabricar un dispositivo semiconductor con tension de encapsulacion reducida.

Country Status (8)

Country Link
EP (1) EP0275588B1 (es)
JP (1) JP2818779B2 (es)
KR (1) KR960016238B1 (es)
CN (1) CN1014380B (es)
BR (1) BR8706895A (es)
DE (1) DE3788119T2 (es)
ES (1) ES2046984T3 (es)
HK (1) HK163795A (es)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0212950A (ja) * 1988-06-30 1990-01-17 Toshiba Corp 半導体装置
NL8902018A (nl) * 1989-08-07 1991-03-01 Philips Nv Halfgeleiderinrichting.
JP3563877B2 (ja) * 1996-06-21 2004-09-08 三菱電機株式会社 半導体装置
TW448524B (en) * 1997-01-17 2001-08-01 Seiko Epson Corp Electronic component, semiconductor device, manufacturing method therefor, circuit board and electronic equipment
JP3223246B2 (ja) * 1997-07-25 2001-10-29 東レ・ダウコーニング・シリコーン株式会社 半導体装置
JP2001284499A (ja) * 2000-03-09 2001-10-12 Lucent Technol Inc 半導体デバイスとその製造方法
GB0018028D0 (en) * 2000-07-24 2000-09-13 Koninkl Philips Electronics Nv Semiconductor devices and their manufacture
WO2005026761A1 (en) * 2003-09-16 2005-03-24 Koninklijke Philips Electronics N.V. A method of manufacturing an electronic device and an electronic device
CN100370580C (zh) * 2004-03-29 2008-02-20 雅马哈株式会社 半导体晶片及其制造方法
CN101091313B (zh) * 2005-11-02 2012-02-15 松下电器产业株式会社 电子部件封装结构
CN102593190B (zh) * 2012-02-13 2015-11-25 贵州雅光电子科技股份有限公司 一种二极管
CN113517205A (zh) * 2020-04-27 2021-10-19 台湾积体电路制造股份有限公司 半导体器件及其形成方法
US11699663B2 (en) 2020-04-27 2023-07-11 Taiwan Semiconductor Manufacturing Company, Ltd. Passivation scheme design for wafer singulation
US11355460B1 (en) * 2020-12-07 2022-06-07 Infineon Technologies Ag Molded semiconductor package with high voltage isolation

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3978578A (en) * 1974-08-29 1976-09-07 Fairchild Camera And Instrument Corporation Method for packaging semiconductor devices
JPS51147962A (en) * 1975-06-02 1976-12-18 Fairchild Camera Instr Co Method of mounting semiconductor devices
JPS5748252A (en) * 1980-09-08 1982-03-19 Nec Corp Semiconductor device and manufacture thereof
JPS5848443A (ja) * 1981-09-17 1983-03-22 Toshiba Corp 樹脂封止型半導体装置
JPS59191353A (ja) * 1983-04-15 1984-10-30 Hitachi Ltd 多層配線構造を有する電子装置
DE3327960A1 (de) * 1983-08-03 1985-02-14 Telefunken electronic GmbH, 7100 Heilbronn Halbleiteranordnung in einem isolierstoffgehaeuse

Also Published As

Publication number Publication date
BR8706895A (pt) 1988-07-26
EP0275588A1 (en) 1988-07-27
JPS63226046A (ja) 1988-09-20
HK163795A (en) 1995-10-27
EP0275588B1 (en) 1993-11-10
KR960016238B1 (en) 1996-12-07
DE3788119T2 (de) 1994-05-11
DE3788119D1 (de) 1993-12-16
CN87108334A (zh) 1988-07-13
CN1014380B (zh) 1991-10-16
JP2818779B2 (ja) 1998-10-30

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