ES2051293T3 - Extractor digital de señal de reloj de bucle de enganche de fase para señales bipolares. - Google Patents

Extractor digital de señal de reloj de bucle de enganche de fase para señales bipolares.

Info

Publication number
ES2051293T3
ES2051293T3 ES88201377T ES88201377T ES2051293T3 ES 2051293 T3 ES2051293 T3 ES 2051293T3 ES 88201377 T ES88201377 T ES 88201377T ES 88201377 T ES88201377 T ES 88201377T ES 2051293 T3 ES2051293 T3 ES 2051293T3
Authority
ES
Spain
Prior art keywords
clock signal
digital phase
signal
signal extractor
loop clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES88201377T
Other languages
English (en)
Inventor
Michele Raucci
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Italtel SpA
Siemens Telecomunicazioni SpA
Original Assignee
Siemens Telecomunicazioni SpA
Societa Italiana Telecomunicazioni Siemens SpA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Telecomunicazioni SpA, Societa Italiana Telecomunicazioni Siemens SpA filed Critical Siemens Telecomunicazioni SpA
Application granted granted Critical
Publication of ES2051293T3 publication Critical patent/ES2051293T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

EL EXTRACTOR DE RELOJ CONSTA DE UN DIVISOR DE FRECUENCIA (30) QUE TOMA LA SEÑAL DE RELOJ A PARTIR DE UNA SEÑAL DE FRECUENCIA QUE ES MULTIPLO DE LA SEÑAL BIPOLAR RECIBIDA. UN PROGRAMA CORRECTOR (24) INCLUIDO EN EL DIVISOR COMPARA EL ESTADO LOGIDO DEL DIVISOR DE FRECUENCIA CON UNA SEÑAL DE DETECCION DE TRANSICION TOMADA POR MUESTREO DE LA SEÑAL BIPOLAR A DICHA FRECUENCIA MULTIPLO Y, SOBRE EL ERROR DE FASE DETECTADO, CONTROLA LA CORRECCION DE FASE DE LA SEÑAL DE RELOJ.
ES88201377T 1987-07-30 1988-07-01 Extractor digital de señal de reloj de bucle de enganche de fase para señales bipolares. Expired - Lifetime ES2051293T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT21527/87A IT1222405B (it) 1987-07-30 1987-07-30 Estrattore digitale di segnale orologio con aggancio e correzione di fase per segnali bipolari

Publications (1)

Publication Number Publication Date
ES2051293T3 true ES2051293T3 (es) 1994-06-16

Family

ID=11183130

Family Applications (1)

Application Number Title Priority Date Filing Date
ES88201377T Expired - Lifetime ES2051293T3 (es) 1987-07-30 1988-07-01 Extractor digital de señal de reloj de bucle de enganche de fase para señales bipolares.

Country Status (9)

Country Link
US (1) US4852124A (es)
EP (1) EP0301616B1 (es)
AT (1) ATE104490T1 (es)
AU (1) AU606963B2 (es)
DE (1) DE3889028T2 (es)
ES (1) ES2051293T3 (es)
IT (1) IT1222405B (es)
NO (1) NO173529C (es)
YU (1) YU137588A (es)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3818843A1 (de) * 1988-06-03 1989-12-07 Standard Elektrik Lorenz Ag Verfahren und schaltungsanordnung zur rueckgewinnung eines bittaktes aus einem empfangenen digitalen nachrichtensignal
US5086435A (en) * 1988-10-17 1992-02-04 Rockwell International Corporation Method and apparatus for detecting signals on digital data systems
US5016259A (en) * 1989-03-03 1991-05-14 The Grass Valley Group, Inc. Low jitter DDFS FSK modulator
US5193087A (en) * 1990-05-16 1993-03-09 Tadiran, Ltd. Electronic digital cross-connect system having bipolar violation transparency
US5197086A (en) * 1990-12-28 1993-03-23 International Business Machines Corporation High speed digital clock synchronizer
US5208833A (en) * 1991-04-08 1993-05-04 Motorola, Inc. Multi-level symbol synchronizer
JP3347848B2 (ja) * 1993-11-08 2002-11-20 株式会社ゼネラル リサーチ オブ エレクトロニックス 多値信号復号回路
US5541967A (en) * 1994-03-09 1996-07-30 National Semiconductor Corporation Fast symbol synchronization for use in conditioning a receiving modem
US6182237B1 (en) * 1998-08-31 2001-01-30 International Business Machines Corporation System and method for detecting phase errors in asics with multiple clock frequencies
US6421785B1 (en) * 1998-11-03 2002-07-16 Intel Corporation Clock selection for processing audio data
SE516280C2 (sv) 2000-04-06 2001-12-10 Ericsson Telefon Ab L M Förfarande och anordning för signalövervakning som baseras på ett glidande fönster
US6343364B1 (en) * 2000-07-13 2002-01-29 Schlumberger Malco Inc. Method and device for local clock generation using universal serial bus downstream received signals DP and DM

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4216544A (en) * 1978-09-19 1980-08-05 Northern Telecom Limited Digital clock recovery circuit
US4280099A (en) * 1979-11-09 1981-07-21 Sperry Corporation Digital timing recovery system
US4456890A (en) * 1982-04-05 1984-06-26 Computer Peripherals Inc. Data tracking clock recovery system using digitally controlled oscillator
US4667333A (en) * 1983-12-22 1987-05-19 Motorola, Inc. Automatic clock recovery circuit
US4628519A (en) * 1984-04-06 1986-12-09 Advanced Micro Devices, Inc. Digital phase-locked loop circuit
IT1214377B (it) * 1984-06-13 1990-01-18 Torino Sip Societa Italiana Pe Circuito numerico per l estrazione di segnali di sincronismo da un flusso seriale di dati codificati
US4694196A (en) * 1984-12-07 1987-09-15 American Telephone And Telegraph Company And At&T Information Systems Clock recovery circuit

Also Published As

Publication number Publication date
IT8721527A0 (it) 1987-07-30
US4852124A (en) 1989-07-25
DE3889028T2 (de) 1994-09-08
AU1861888A (en) 1989-02-02
NO173529B (no) 1993-09-13
NO883325D0 (no) 1988-07-27
AU606963B2 (en) 1991-02-21
EP0301616A3 (en) 1990-01-31
NO173529C (no) 1993-12-22
ATE104490T1 (de) 1994-04-15
IT1222405B (it) 1990-09-05
YU137588A (en) 1991-02-28
EP0301616B1 (en) 1994-04-13
EP0301616A2 (en) 1989-02-01
DE3889028D1 (de) 1994-05-19
NO883325L (no) 1989-01-31

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