ES2063978T3 - Procedimiento para la generacion de una magnitud de ajuste y circuito para la ejecucion del procedimiento. - Google Patents

Procedimiento para la generacion de una magnitud de ajuste y circuito para la ejecucion del procedimiento.

Info

Publication number
ES2063978T3
ES2063978T3 ES90912796T ES90912796T ES2063978T3 ES 2063978 T3 ES2063978 T3 ES 2063978T3 ES 90912796 T ES90912796 T ES 90912796T ES 90912796 T ES90912796 T ES 90912796T ES 2063978 T3 ES2063978 T3 ES 2063978T3
Authority
ES
Spain
Prior art keywords
procedure
circuit
magnitude
execution
adjustment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES90912796T
Other languages
English (en)
Inventor
Werner Scholz
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Deutsche Thomson Brandt GmbH
Original Assignee
Deutsche Thomson Brandt GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Deutsche Thomson Brandt GmbH filed Critical Deutsche Thomson Brandt GmbH
Application granted granted Critical
Publication of ES2063978T3 publication Critical patent/ES2063978T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M5/00—Conversion of the form of the representation of individual digits
    • H03M5/02—Conversion to or from representation by pulses
    • H03M5/04—Conversion to or from representation by pulses the pulses having two levels
    • H03M5/14—Code representation, e.g. transition, for a given bit cell depending on the information in one or more adjacent bit cells, e.g. delay modulation code, double density code
    • H03M5/145—Conversion to or from block codes or representations thereof
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H04L7/0083—Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Theoretical Computer Science (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Manipulation Of Pulses (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Testing, Inspecting, Measuring Of Stereoscopic Televisions And Televisions (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Radar Systems Or Details Thereof (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Indexing, Searching, Synchronizing, And The Amount Of Synchronization Travel Of Record Carriers (AREA)
  • Details Of Television Scanning (AREA)

Abstract

EL FIN DE LA INVENCION ES OBTENER, UTILIZANDO UN CIRCUITO DIGITAL, A PARTIR DE UNA SEÑAL BINARIA UNA CANTIDAD DE CONTROL (G) QUE INDICA SI LA SEÑAL BINARIA CONTIENE UNA SEÑAL DESEADA O SIMPLEMENTE UNA SEÑAL DE INTERFERENCIA. EN UNA PRIMERA ETAPA (24), SE COMPRUEBA LA LONGITUD DE LA PASADA Y, EN UNA SEGUNDA ETAPA (25, 26), SE CONTROLA LA DISTANCIA ENTRE LOS REBASES DE LA LONGITUD DE PASADA. EL CIRCUITO SE UTILIZA EN PARTICULAR PARA DETECTAR EL PRINCIPIO DE LA SEÑAL DESEADA EN UN GRABADOR DIGITAL.
ES90912796T 1989-08-30 1990-08-22 Procedimiento para la generacion de una magnitud de ajuste y circuito para la ejecucion del procedimiento. Expired - Lifetime ES2063978T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE3928676A DE3928676A1 (de) 1989-08-30 1989-08-30 Schaltung zur erkennung eines nutzsignals in einem binaeren signal

Publications (1)

Publication Number Publication Date
ES2063978T3 true ES2063978T3 (es) 1995-01-16

Family

ID=6388180

Family Applications (1)

Application Number Title Priority Date Filing Date
ES90912796T Expired - Lifetime ES2063978T3 (es) 1989-08-30 1990-08-22 Procedimiento para la generacion de una magnitud de ajuste y circuito para la ejecucion del procedimiento.

Country Status (9)

Country Link
EP (1) EP0489785B1 (es)
JP (1) JP2911599B2 (es)
KR (1) KR100196617B1 (es)
AT (1) ATE113771T1 (es)
AU (1) AU6286890A (es)
DE (2) DE3928676A1 (es)
ES (1) ES2063978T3 (es)
HK (1) HK50096A (es)
WO (1) WO1991003879A1 (es)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050085072A1 (en) 2003-10-20 2005-04-21 Kim Hyun T. Formation of self-aligned contact plugs

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5895448A (ja) * 1981-12-02 1983-06-07 Matsushita Electric Ind Co Ltd フェ−ズ・ロックド・ル−プ回路
JPS58220226A (ja) * 1982-06-15 1983-12-21 Toshiba Corp 位相ロツクル−プ制御回路
JPS60113367A (ja) * 1983-11-23 1985-06-19 Sony Corp デイスク・プレ−ヤのクロツク再生回路
JPS61258534A (ja) * 1985-05-11 1986-11-15 Victor Co Of Japan Ltd デジタル信号復調装置
DE3634751A1 (de) * 1986-10-11 1988-04-14 Thomson Brandt Gmbh Phasendiskriminator, insbesondere fuer eine pll-schaltung
DE3639886A1 (de) * 1986-11-21 1988-06-01 Thomson Brandt Gmbh Schaltung zur verarbeitung digitaler signale

Also Published As

Publication number Publication date
DE3928676A1 (de) 1991-03-07
JP2911599B2 (ja) 1999-06-23
ATE113771T1 (de) 1994-11-15
EP0489785B1 (de) 1994-11-02
WO1991003879A1 (de) 1991-03-21
AU6286890A (en) 1991-04-08
DE59007655D1 (de) 1994-12-08
JPH05500141A (ja) 1993-01-14
EP0489785A1 (de) 1992-06-17
HK50096A (en) 1996-03-29
KR100196617B1 (ko) 1999-06-15

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