ES2076447T3 - Procedimiento para la obtencion de placas conductoras. - Google Patents

Procedimiento para la obtencion de placas conductoras.

Info

Publication number
ES2076447T3
ES2076447T3 ES91119852T ES91119852T ES2076447T3 ES 2076447 T3 ES2076447 T3 ES 2076447T3 ES 91119852 T ES91119852 T ES 91119852T ES 91119852 T ES91119852 T ES 91119852T ES 2076447 T3 ES2076447 T3 ES 2076447T3
Authority
ES
Spain
Prior art keywords
procedure
printed circuit
zones
radiation
contacted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES91119852T
Other languages
English (en)
Inventor
Hartmut Dipl-Ing Fh Schumacher
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Siemens Corp
Original Assignee
Siemens AG
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG, Siemens Corp filed Critical Siemens AG
Application granted granted Critical
Publication of ES2076447T3 publication Critical patent/ES2076447T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/027—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed by irradiation, e.g. by photons, alpha or beta particles
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09118—Moulded substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/0929—Conductive planes
    • H05K2201/09363—Conductive planes wherein only contours around conductors are removed for insulation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/10—Using electric, magnetic and electromagnetic fields; Using laser light
    • H05K2203/107—Using laser light
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
    • H05K3/181—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing of the conductive pattern
    • H05K3/241—Reinforcing of the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H05K3/426—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in substrates without metal

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Laminated Bodies (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)

Abstract

LA INVENCION SE REFIERA A UN PROCEDIMIENTO PARA LA FABRICACION DE PLACAS DE CIRCUITOS IMPRESOS, CON LOS SIGUIENTES PASOS DE PROCEDIMIENTO: A) LA PLACA DE CIRCUITO IMPRESO (1) SE TRATA PREVIAMENTE PARA LA ADHERENCIA DE LA CAPA METALICA (3); B) SE APLICA UNA PRIMERA CAPA METALICA (3) DELGADA; C) LA CAPA METALICA (3) ES ELIMINADA DE LAS ZONAS LIMITROFES INMEDIATAS A LA POSTERIOR SUPERFICIE TEXTURADA POR MEDIO DE RADIACION ELECTROMAGNETICA (S), Y PRECISAMENTE MEDIANTE TAL AJUSTE Y CONDUCCION DE LA RADIACION (S) QUE SE PRODUCE UNA SEPARACION DE LAS PISTAS Y UNA ACTUACION NO PERJUDICIAL DE LAS CONSECUENCIAS DEL TRATAMIENTO DEL CIRCUITO IMPRESO; D) LAS ZONAS DE LA CAPA METALICA (3) CORRESPONDIENTES A LA SUPERFICIE TEXTURADA SON CONTACTADAS CATODICAMENTE; E) SOBRE LAS ZONAS CATODICAS CONTACTADAS SE APLICA UNA SEGUNDA CAPA METALICA (7) EN UN BAÑO DE SEPARACION METALICO GALVANICO. POR ELLO ES POSIBLE PASAR CON POCOS PASOS DEL PROCEDIMIENTO. SE PRESCINDE DE LA APLICACION DE CAPAS RESISTENTES Y DEL PROCEDIMIENTO DE CAUSTICACION.
ES91119852T 1991-11-21 1991-11-21 Procedimiento para la obtencion de placas conductoras. Expired - Lifetime ES2076447T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP19910119852 EP0543045B1 (de) 1991-11-21 1991-11-21 Verfahren zur Herstellung von Leiterplatten

Publications (1)

Publication Number Publication Date
ES2076447T3 true ES2076447T3 (es) 1995-11-01

Family

ID=8207360

Family Applications (1)

Application Number Title Priority Date Filing Date
ES91119852T Expired - Lifetime ES2076447T3 (es) 1991-11-21 1991-11-21 Procedimiento para la obtencion de placas conductoras.

Country Status (3)

Country Link
EP (1) EP0543045B1 (es)
DE (1) DE59106557D1 (es)
ES (1) ES2076447T3 (es)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0711102B1 (en) * 1992-11-19 2000-09-27 Polyplastics Co. Ltd. Method for forming a conductive circuit on the surface of a molded product
JP3159841B2 (ja) * 1993-08-26 2001-04-23 ポリプラスチックス株式会社 レーザーによる回路形成方法及び導電回路形成部品
JP3153682B2 (ja) * 1993-08-26 2001-04-09 松下電工株式会社 回路板の製造方法
US5863405A (en) * 1994-05-18 1999-01-26 Polyplastics Co., Ltd. Process for forming conductive circuit on the surface of molded article
US8621749B2 (en) 2010-03-12 2014-01-07 Taiwan Green Point Enterprises Co., Ltd Non-deleterious technique for creating continuous conductive circuits

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ATE56050T1 (de) * 1987-04-24 1990-09-15 Siemens Ag Verfahren zur herstellung von leiterplatten.
US4943346A (en) * 1988-09-29 1990-07-24 Siemens Aktiengesellschaft Method for manufacturing printed circuit boards
US4898648A (en) * 1988-11-15 1990-02-06 Pacific Bell Method for providing a strengthened conductive circuit pattern
DE3843230C1 (en) * 1988-12-22 1989-09-21 W.C. Heraeus Gmbh, 6450 Hanau, De Process for making a metallic pattern on a base, in particular for the laser structuring of conductor tracks

Also Published As

Publication number Publication date
EP0543045B1 (de) 1995-09-20
EP0543045A1 (de) 1993-05-26
DE59106557D1 (de) 1995-10-26

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