ES2088923T3 - Dispositivo y metodo de seleccion de tiempos de retardo de impulsos de transferencia. - Google Patents

Dispositivo y metodo de seleccion de tiempos de retardo de impulsos de transferencia.

Info

Publication number
ES2088923T3
ES2088923T3 ES90108918T ES90108918T ES2088923T3 ES 2088923 T3 ES2088923 T3 ES 2088923T3 ES 90108918 T ES90108918 T ES 90108918T ES 90108918 T ES90108918 T ES 90108918T ES 2088923 T3 ES2088923 T3 ES 2088923T3
Authority
ES
Spain
Prior art keywords
speed circuitry
circuitry
delay stage
high speed
low speed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES90108918T
Other languages
English (en)
Inventor
Milton Rodney Briscoe
Raymond Eugene Tyrrell
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alcatel Lucent NV
Original Assignee
Alcatel NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel NV filed Critical Alcatel NV
Application granted granted Critical
Publication of ES2088923T3 publication Critical patent/ES2088923T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/131—Digitally controlled
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0602—Systems characterised by the synchronising information used
    • H04J3/0605—Special codes used as synchronising signal
    • H04J3/0608—Detectors therefor, e.g. correlators, state machines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/042—Detectors therefor, e.g. correlators, state machines

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Information Transfer Systems (AREA)
  • Pulse Circuits (AREA)
  • Investigating Or Analyzing Materials By The Use Of Ultrasonic Waves (AREA)
  • Networks Using Active Elements (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

UN SELECTOR DE FASES DE RETARDO DE CIRCUITO FILTRO DE TRANSFERENCIA ASEGURA LA TRANSFERENCIA EXACTA DE DATOS DESDE CIRCUITERIA DE GRAN VELOCIDAD (25) A CIRCUITERIA (27) DE BAJA VELOCIDAD, A TRAVES DEL USO DE UN MODULO (34) DE FASES DE RETARDO, COMPRENDIENDO UNA PLURALIDAD DE FASES (36), Y UN MULTIPLEXOR (38) ASOCIADO, PARA SELECCIONAR UNO DE LAS FASES DE RETARDO, PARA PROPORCIONAR LA RECEPCION EXACTA DE DATOS PARALELOS MEDIANTE LA CIRCUITERIA (27) DE BAJA VELOCIDAD, DESDE LA CIRCUITERIA (25) DE ALTA VELOCIDAD. EL SELECTOR DE FASES DE RETARDO DE CIRCUITO FILTRO DE TRANSFERENCIA INCORPORA UN MODULO (42) DE IDENTIFICACION DE CANAL DE SINCRONIZACION, PARA DETECTAR LA INFORMACION DEL CANAL DE INFORMACION EN LOS CUADROS DE DATOS TRANSFERIDOS DESDE LA CIRCUITERIA (25) DE ALTA VELOCIDAD A LA CIRCUITERIA (27) DE BAJA VELOCIDAD, Y TAMBIEN INCLUYE LA CIRCUITERIA (52) DE CONTROL PARA AJUSTAR LA FASE DE RETARDO SELECCIONADA, HASTA QUE SE DETECTA LA IDENTIFICACION (42) DEL CANAL DE SINCRONIZACION.
ES90108918T 1989-05-12 1990-05-11 Dispositivo y metodo de seleccion de tiempos de retardo de impulsos de transferencia. Expired - Lifetime ES2088923T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/351,016 US5060239A (en) 1989-05-12 1989-05-12 Transfer strobe time delay selector and method for performing same

Publications (1)

Publication Number Publication Date
ES2088923T3 true ES2088923T3 (es) 1996-10-01

Family

ID=23379231

Family Applications (1)

Application Number Title Priority Date Filing Date
ES90108918T Expired - Lifetime ES2088923T3 (es) 1989-05-12 1990-05-11 Dispositivo y metodo de seleccion de tiempos de retardo de impulsos de transferencia.

Country Status (7)

Country Link
US (1) US5060239A (es)
EP (1) EP0397198B1 (es)
AT (1) ATE134463T1 (es)
AU (1) AU626018B2 (es)
CA (1) CA2016616C (es)
DE (1) DE69025422T2 (es)
ES (1) ES2088923T3 (es)

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CA2023998A1 (en) * 1989-11-13 1991-05-14 Thomas F. Lewis Apparatus and method for guaranteeing strobe separation timing
US5199046A (en) * 1991-09-09 1993-03-30 Codex Corporation First and second digital rate converter synchronization device and method
US5253254A (en) * 1991-09-18 1993-10-12 Dsc Communications Corporation Telecommunications system with arbitrary alignment parallel framer
JPH05168073A (ja) * 1991-12-19 1993-07-02 Mitsubishi Electric Corp 共通線信号挿抜装置
US5481675A (en) * 1992-05-12 1996-01-02 International Business Machines Corporation Asynchronous serial communication system for delaying with software dwell time a receiving computer's acknowledgement in order for the transmitting computer to see the acknowledgement
KR950008661B1 (ko) * 1993-05-20 1995-08-04 현대전자산업주식회사 버스 다중화 회로
US5708817A (en) * 1995-05-31 1998-01-13 Apple Computer, Inc. Programmable delay of an interrupt
JP3441589B2 (ja) * 1996-02-29 2003-09-02 シャープ株式会社 同期検出復調回路
SE506817C2 (sv) * 1996-06-20 1998-02-16 Ericsson Telefon Ab L M Seriell-parallell- och parallell-seriellomvandlare innefattande frekvensdelare
KR100200968B1 (ko) * 1996-10-17 1999-06-15 윤종용 화상형성장치의 호스트 인터페이스회로
FR2756120B1 (fr) * 1996-11-19 1999-02-05 Sgs Thomson Microelectronics Dispositif de conversion serie/parallele d'un signal haute frequence de faible amplitude
US5999995A (en) * 1996-12-27 1999-12-07 Oki Data Corporation Systems for adjusting a transfer rate between a host and a peripheral based on a calculation of the processing rate of the host
JPH11298306A (ja) * 1998-04-16 1999-10-29 Nec Corp 半導体装置および遅延設定方法
US6121808A (en) * 1998-05-18 2000-09-19 National Semiconductor Corporation DLL calibrated phase multiplexer and interpolator
US6529570B1 (en) * 1999-09-30 2003-03-04 Silicon Graphics, Inc. Data synchronizer for a multiple rate clock source and method thereof
US7198197B2 (en) * 2002-11-05 2007-04-03 Rambus, Inc. Method and apparatus for data acquisition
US7171321B2 (en) * 2004-08-20 2007-01-30 Rambus Inc. Individual data line strobe-offset control in memory systems
US7543172B2 (en) 2004-12-21 2009-06-02 Rambus Inc. Strobe masking in a signaling system having multiple clock domains
BRPI0519844A2 (pt) * 2005-01-14 2009-03-17 Thomson Licensing aparelho e método para uso em um receptor
CN101103547A (zh) * 2005-01-14 2008-01-09 汤姆森特许公司 使用执行扰码确定的瑞克搜索器的小区搜索
US20080137846A1 (en) * 2005-01-14 2008-06-12 Alton Shelborne Keel Ram- Based Scrambling Code Generator for Cdma
US8059776B2 (en) * 2005-01-14 2011-11-15 Thomson Licensing Method and system for sub-chip resolution for secondary cell search
CN101103546B (zh) * 2005-01-14 2011-04-06 汤姆森特许公司 码分多址系统的高效的最大比合并器
US7688672B2 (en) * 2005-03-14 2010-03-30 Rambus Inc. Self-timed interface for strobe-based systems
FR2895173B1 (fr) * 2005-12-20 2008-01-25 Thales Sa Interface de transmission de donnees numeriques synchrones
US8121237B2 (en) 2006-03-16 2012-02-21 Rambus Inc. Signaling system with adaptive timing calibration
KR100841456B1 (ko) 2006-10-19 2008-06-26 고려대학교 산학협력단 지연 부정합을 보상하는 직렬화기
WO2008104958A2 (en) * 2007-03-01 2008-09-04 Nxp B.V. Data recovery system and method
US8687441B2 (en) * 2011-04-13 2014-04-01 Himax Technologies Limited Method for searching optimum value of memory
CN114691558B (zh) * 2021-10-20 2023-06-20 澜起电子科技(上海)有限公司 低延迟重定时器及延迟控制方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3225365A1 (de) * 1982-07-07 1984-01-12 Robert Bosch Gmbh, 7000 Stuttgart Verfahren zur wandlung serieller datensignale
FR2538647B1 (fr) * 1982-12-28 1990-01-12 Billy Jean Claude Circuit de demultiplexage d'un signal numerique en trames et a haut debit
US4596026A (en) * 1983-05-09 1986-06-17 Raytheon Company Asynchronous data clock generator
FR2548490A1 (fr) * 1983-06-30 1985-01-04 Thomson Csf Circuit programmable de transformation serie-parallele d'un signal numerique, et son application a un recepteur de signaux video numeriques
US4580279A (en) * 1984-04-16 1986-04-01 At&T Bell Laboratories Elastic store slip control and maintenance circuit
US4617658A (en) * 1985-04-17 1986-10-14 Bell Communications Research, Inc. Frame arrangement for multiplexing a plurality of subchannels onto a fixed rate channel
EP0262457A1 (de) * 1986-09-26 1988-04-06 Siemens Aktiengesellschaft Anordnung zum Synchronisieren eines aus einem Datenbitstrom abgeleiteten Bytetaktes mit einem byteorientierten Verarbeitungstakt einer Endeinrichtung
JPH0728280B2 (ja) * 1986-10-17 1995-03-29 富士通株式会社 多重マルチフレ−ム同期検出回路
US4887279A (en) * 1988-09-19 1989-12-12 Tektronix, Inc. Timing measurement for jitter display

Also Published As

Publication number Publication date
DE69025422T2 (de) 1996-07-25
US5060239A (en) 1991-10-22
EP0397198A3 (en) 1991-09-18
DE69025422D1 (de) 1996-03-28
EP0397198B1 (en) 1996-02-21
AU626018B2 (en) 1992-07-23
AU5468190A (en) 1990-11-15
ATE134463T1 (de) 1996-03-15
CA2016616A1 (en) 1990-11-12
EP0397198A2 (en) 1990-11-14
CA2016616C (en) 1998-06-23

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