ES2095924T3 - Dispositivo para el intercambio dinamico de procesador de servicio. - Google Patents

Dispositivo para el intercambio dinamico de procesador de servicio.

Info

Publication number
ES2095924T3
ES2095924T3 ES91402069T ES91402069T ES2095924T3 ES 2095924 T3 ES2095924 T3 ES 2095924T3 ES 91402069 T ES91402069 T ES 91402069T ES 91402069 T ES91402069 T ES 91402069T ES 2095924 T3 ES2095924 T3 ES 2095924T3
Authority
ES
Spain
Prior art keywords
service processor
service
cmu
maintenance unit
program
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES91402069T
Other languages
English (en)
Inventor
Jean-Francois Bonnafoux
Robert Flon
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull SAS
Original Assignee
Bull SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bull SAS filed Critical Bull SAS
Application granted granted Critical
Publication of ES2095924T3 publication Critical patent/ES2095924T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/273—Tester hardware, i.e. output processing circuits
    • G06F11/2736—Tester hardware, i.e. output processing circuits using a dedicated service processor for test
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/32—Monitoring with visual or acoustical indication of the functioning of the machine

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Hardware Redundancy (AREA)
  • Multi Processors (AREA)
  • Exchange Systems With Centralized Control (AREA)
  • Telephonic Communication Services (AREA)
  • Computer And Data Communications (AREA)

Abstract

LA PRESENTE INVENCION TRATA DE UNA ARQUITECTURA PARA CAMBIO DINAMICO DE PROCESADOR DE SERVICIO. ARQUITECTURA PARA CAMBIO DINAMICO DE PROCESADOR DE SERVICIO, CONTENIENDO UN PRIMER PROCESADOR DE SERVICIO CONECTADO POR UNA RED Y UNA UNIDAD DE MANTENIMIENTO (CMU) A UN SISTEMA CENTRAL (4), SUSODICHO PROCESADOR DE SERVICIO (1) ESTA CONECTADO A UN SEGUNDO PROCESADOR DE SERVICIO (2) POR LA RED Y LA UNIDAD DE MANTENIMIENTO (CMU), CARACTERIZADA EN LO QUE CADA PROCESADOR DE SERVICIO CONTIENE ADEMAS DE LOS PROGRAMAS DE SISTEMA DE EXPLOTACION, UN PROGRAMA SUPERVISOR Y AL MENOS UN SERVICIO DESCOMPUESTO EN DOS APLICACIONES, UNA "CUERPO" COMPUESTA DEL ALGORITMO DEL PROGRAMA, Y LA OTRA "PRESENTACION" CONTENIENDO EL INTERFAZ CON EL OPERADOR PERMITIENDO UNA VISUALIZACION DEL TIPO VENTANA CON UNA BARRA DE MENU, Y MEDIOS MSH (10, 20) DE TRATAMIENTO DE COMUNICACIONES CON LOS OTROS PROCESADORES DE SERVICIO, POR EL INTERMEDIO DE LA UNIDAD DE MANTENIMIENTO (CMU), UN PROGRAMA SUPERVISOR ADMINISTRANDO LOS NUMEROS DEINSTANCIA DE LOS SERVICIOS E INICIANDO LOS SERVICIOS, SUSODICHO PROGRAMA SUPERVISOR TENIENDO ACCESO A UNA TABLA DE CONFIGURACION DEL SISTEMA (IRT, ECF).
ES91402069T 1990-08-09 1991-07-24 Dispositivo para el intercambio dinamico de procesador de servicio. Expired - Lifetime ES2095924T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9010180A FR2665778B1 (fr) 1990-08-09 1990-08-09 Architecture pour echange dynamique de processeur de service.

Publications (1)

Publication Number Publication Date
ES2095924T3 true ES2095924T3 (es) 1997-03-01

Family

ID=9399570

Family Applications (1)

Application Number Title Priority Date Filing Date
ES91402069T Expired - Lifetime ES2095924T3 (es) 1990-08-09 1991-07-24 Dispositivo para el intercambio dinamico de procesador de servicio.

Country Status (8)

Country Link
EP (1) EP0470880B1 (es)
JP (1) JPH0664570B2 (es)
AT (1) ATE144847T1 (es)
CA (1) CA2067189C (es)
DE (1) DE69122924T2 (es)
ES (1) ES2095924T3 (es)
FR (1) FR2665778B1 (es)
WO (1) WO1992002878A1 (es)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5513351A (en) * 1994-07-28 1996-04-30 International Business Machines Corporation Protecting a system during system maintenance by usage of temporary filenames in an alias table

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4014005A (en) * 1976-01-05 1977-03-22 International Business Machines Corporation Configuration and control unit for a heterogeneous multi-system
US4455601A (en) * 1981-12-31 1984-06-19 International Business Machines Corporation Cross checking among service processors in a multiprocessor system
JPS6272248A (ja) * 1985-09-25 1987-04-02 Hitachi Ltd デ−タ伝送システムの現用予備切替方法
US4894828A (en) * 1987-12-22 1990-01-16 Amdahl Corporation Multiple sup swap mechanism
FR2633413B1 (fr) * 1988-06-22 1994-07-08 Bull Sa Procede pour la generation de fenetres de dialogue visualisables sur l'ecran d'un systeme informatique et dispositif pour mettre en oeuvre ce procede
FR2658934B1 (fr) * 1990-02-28 1992-04-30 Bull Sa Architecture de systeme et utilisation de cette architecture dans un procede de remplacement de cartes.

Also Published As

Publication number Publication date
JPH04505680A (ja) 1992-10-01
EP0470880A1 (fr) 1992-02-12
FR2665778B1 (fr) 1993-06-18
CA2067189C (fr) 1995-05-23
ATE144847T1 (de) 1996-11-15
WO1992002878A1 (fr) 1992-02-20
CA2067189A1 (fr) 1992-02-10
DE69122924D1 (de) 1996-12-05
JPH0664570B2 (ja) 1994-08-22
EP0470880B1 (fr) 1996-10-30
DE69122924T2 (de) 1997-03-06
FR2665778A1 (fr) 1992-02-14

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