ES2098791T3 - Disposicion con varios usuarios activos y pasivos del bus. - Google Patents

Disposicion con varios usuarios activos y pasivos del bus.

Info

Publication number
ES2098791T3
ES2098791T3 ES93924011T ES93924011T ES2098791T3 ES 2098791 T3 ES2098791 T3 ES 2098791T3 ES 93924011 T ES93924011 T ES 93924011T ES 93924011 T ES93924011 T ES 93924011T ES 2098791 T3 ES2098791 T3 ES 2098791T3
Authority
ES
Spain
Prior art keywords
bus users
pct
memory
bus
master
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES93924011T
Other languages
English (en)
Inventor
Michael Abert
Siegfried Block
Johannes Bozenhardt
Franz Leigsnering
Werner Pfatteicher
Franz-Clemens Schewe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Siemens Corp
Original Assignee
Siemens AG
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE4237259A external-priority patent/DE4237259A1/de
Priority claimed from DE19934304259 external-priority patent/DE4304259A1/de
Application filed by Siemens AG, Siemens Corp filed Critical Siemens AG
Application granted granted Critical
Publication of ES2098791T3 publication Critical patent/ES2098791T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G06F13/378—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a parallel poll method
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Small-Scale Networks (AREA)
  • Bus Control (AREA)
  • Memory System (AREA)
  • Medicines Containing Antibodies Or Antigens For Use As Internal Diagnostic Agents (AREA)
  • Multi Processors (AREA)

Abstract

LA INVENCION SE REFIERE A UNA DISPOSICION CON PARTICIPANTES (MP1, MP2, SP1, SP2) DE BUS PASIVOS Y ACTIVOS MULTIPLES, CADA UNO DE LOS CUALES ESTA LOCALIZADO EN UNA MEMORIA (S1, S2, SS1, SS2), CON SU PROPIA ZONA DE MEMORIA (SB1, SB2, SB3, SB4), DONDE CADA UNO DE LOS UTILIZADORES BUS (MP1, MP2, SP1, SP2) HA CONSEGUIDO ACCESO A SU PROPIA AREA DE MEMORIA (SB1, SB2, SB3, SB4) Y CADA PARTICIPANTE (MP1, MP2) DE BUS ACTIVO DISPONE DE ACCESO ESCRITO A CADA AREA (SB1, SB2, SB3, SB4) DE MEMORIA. UNA LINEA (ML) DE CONTROL ESTA PREVISTA PARA ENVIAR UNA SEÑAL (SR) INDICATIVA QUE INDICA AL PARTICIPANTE (MP1, MP2) DE BUS ACTIVO EL ACCESO A LAS AREAS (SB1, SB2, SB3, SB4) DE MEMORIA SIN LOS DATOS EN LAS AREAS (SB1, SB2, SB3, SB4) DE MEMORIA, DADO QUE LA SEÑAL (SR) DE RESPUESTA DISPONE DE UNA SITUACION DOMINANTE Y RECESIVA Y, FUERA DE LO CICLOS DE ACCESO DE TODOS LOS PARTICIPANTES BUS, PRODUCE UNA SITUACION DOMINANTE, DURANTE UN CICLO DE ACCESO A LAS AREAS (SB1, SB2, SB3, SB4) DE MEMORIA SOLAMENTE DE LOS PARTICIPANTES (MP1, MP2, SP1, SP2) DE BUS EN CUYAS AREAS (SB1, SB2, SB3, SB4) DE MEMORIA LOS DATOS NO HAN SIDO TODAVIA ESCRITOS PARA PRODUCIR UNA SEÑAL DE ESTE TIPO. LA INVENCION DR UTILIZA EN SISTEMAS DE AUTOMOCION.
ES93924011T 1992-11-04 1993-10-29 Disposicion con varios usuarios activos y pasivos del bus. Expired - Lifetime ES2098791T3 (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE4237259A DE4237259A1 (de) 1992-11-04 1992-11-04 Anordnung zur Datenübertragung mit einem parallelen Bussystem
DE19934304259 DE4304259A1 (de) 1993-02-12 1993-02-12 Anordnung mit mehreren aktiven und passiven Busteilnehmern

Publications (1)

Publication Number Publication Date
ES2098791T3 true ES2098791T3 (es) 1997-05-01

Family

ID=25920125

Family Applications (1)

Application Number Title Priority Date Filing Date
ES93924011T Expired - Lifetime ES2098791T3 (es) 1992-11-04 1993-10-29 Disposicion con varios usuarios activos y pasivos del bus.

Country Status (7)

Country Link
US (1) US5761451A (es)
EP (1) EP0667015B1 (es)
JP (1) JPH07508845A (es)
AT (1) ATE149713T1 (es)
DE (2) DE9321323U1 (es)
ES (1) ES2098791T3 (es)
WO (1) WO1994010632A1 (es)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6105152A (en) * 1993-04-13 2000-08-15 Micron Technology, Inc. Devices and methods for testing cell margin of memory devices
US5944822A (en) * 1997-08-18 1999-08-31 Motorola, Inc. Channel isolation arrangement and method for dissociated data
US6421755B1 (en) 1999-05-26 2002-07-16 Dell Usa, L.P. System resource assignment for a hot inserted device
JP3791742B2 (ja) * 1999-05-28 2006-06-28 株式会社沖データ Ｐｃｉバス制御システム
FR2830152B1 (fr) * 2001-09-27 2004-08-20 Airbus France Bus de terrain deterministe et procede de gestion d'un tel bus
KR101153712B1 (ko) * 2005-09-27 2012-07-03 삼성전자주식회사 멀티-포트 ｓｄｒａｍ 엑세스 제어장치와 제어방법
US8185680B2 (en) * 2006-02-06 2012-05-22 Standard Microsystems Corporation Method for changing ownership of a bus between master/slave devices
DE102008034445B4 (de) * 2008-07-24 2010-03-11 Diehl Aerospace Gmbh Verfahren und Einrichtung zum Erfassen von Bus-Teilnehmern
DE102011003729A1 (de) * 2010-02-08 2011-08-11 Robert Bosch GmbH, 70469 Neuartige Schaltung und Methode zur Kommunikation über eine einzelne Leitung

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5868346A (ja) * 1981-10-18 1983-04-23 Toshiba Corp デ−タ伝送システム
US4724519A (en) * 1985-06-28 1988-02-09 Honeywell Information Systems Inc. Channel number priority assignment apparatus
DE3621105A1 (de) * 1986-06-24 1988-01-07 Vdo Schindling Verfahren zur uebertragung von informationen zwischen selbstaendigen teilnehmern eines systems ueber eine serielle schnittstelle und anordnung zur durchfuehrung des verfahrens
US5404327A (en) * 1988-06-30 1995-04-04 Texas Instruments Incorporated Memory device with end of cycle precharge utilizing write signal and data transition detectors
US5179713A (en) * 1989-11-13 1993-01-12 Chips And Technologies, Inc. Apparatus for allowing external control of local bus read using zero wait stats input of combined I/O and DRAM controller
JP2820752B2 (ja) * 1990-01-19 1998-11-05 日本電信電話株式会社 密結合マルチプロセッサシステムにおけるキャッシュメモリ一致制御方法
JPH0823859B2 (ja) * 1990-09-28 1996-03-06 インターナショナル・ビジネス・マシーンズ・コーポレイション データ処理システム
US5367678A (en) * 1990-12-06 1994-11-22 The Regents Of The University Of California Multiprocessor system having statically determining resource allocation schedule at compile time and the using of static schedule with processor signals to control the execution time dynamically
US5295259A (en) * 1991-02-05 1994-03-15 Advanced Micro Devices, Inc. Data cache and method for handling memory errors during copy-back
US5249297A (en) * 1991-04-29 1993-09-28 Hewlett-Packard Company Methods and apparatus for carrying out transactions in a computer system
US5432911A (en) * 1991-07-15 1995-07-11 Matsushita Electric Works, Ltd. Controllers request access within one bus cycle causing hardware-wait to stall second controller when first controller is accessing and second controller is still requesting access
US5345562A (en) * 1992-02-12 1994-09-06 Industrial Technology Research Institute Data bus arbitration for split transaction computer bus
DE4219005A1 (de) * 1992-06-10 1993-12-16 Siemens Ag Rechnersystem
US5475850A (en) * 1993-06-21 1995-12-12 Intel Corporation Multistate microprocessor bus arbitration signals

Also Published As

Publication number Publication date
EP0667015B1 (de) 1997-03-05
DE9321323U1 (de) 1997-04-10
JPH07508845A (ja) 1995-09-28
DE59305660D1 (de) 1997-04-10
US5761451A (en) 1998-06-02
ATE149713T1 (de) 1997-03-15
WO1994010632A1 (de) 1994-05-11
EP0667015A1 (de) 1995-08-16

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