ES2148492T3 - Ordenador de arquitectura harvard superescalar masivamente multiplexado. - Google Patents

Ordenador de arquitectura harvard superescalar masivamente multiplexado.

Info

Publication number
ES2148492T3
ES2148492T3 ES95909225T ES95909225T ES2148492T3 ES 2148492 T3 ES2148492 T3 ES 2148492T3 ES 95909225 T ES95909225 T ES 95909225T ES 95909225 T ES95909225 T ES 95909225T ES 2148492 T3 ES2148492 T3 ES 2148492T3
Authority
ES
Spain
Prior art keywords
cpu
computational circuits
circuits
general purpose
computational
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES95909225T
Other languages
English (en)
Inventor
Wayne P Dupree
Stephen G Churchill
Jeffry R Gallant
Larry A Root
William J Bressette
Robert A Orr Iii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dow Chemical Co
Original Assignee
Dow Chemical Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dow Chemical Co filed Critical Dow Chemical Co
Application granted granted Critical
Publication of ES2148492T3 publication Critical patent/ES2148492T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7828—Architectures of general purpose stored program computers comprising a single central processing unit without memory
    • G06F15/7832—Architectures of general purpose stored program computers comprising a single central processing unit without memory on one IC chip (single chip microprocessors)
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30141—Implementation provisions of register files, e.g. ports
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Complex Calculations (AREA)
  • Advance Control (AREA)
  • Multi Processors (AREA)
  • Machine Translation (AREA)
  • Executing Machine-Instructions (AREA)
  • Microcomputers (AREA)

Abstract

SE PRESENTA UNA UNIDAD CENTRAL DE PROCESAMIENTO (CPU) MASIVAMENTE MULTIPLEXADO QUE TIENE UNA PLURALIDAD DE CIRCUITOS COMPUTACIONALES INDEPENDIENTES, UN BUS DE RESULTADOS INTERNOS SEPARADO PARA TRANSMITIR LA SALIDA RESULTANTE DE CADA UNO DE ESTOS CIRCUITOS COMPUTACIONALES, Y UNA PLURALIDAD DE REGISTROS DE PROPOSITO GENERAL ACOPLADOS A CADA UNO DE LOS CIRCUITOS COMPUTACIONALES. CADA UNO DE LOS REGISTROS DE PROPOSITOS GENERAL TIENEN PUERTOS DE ENTRADA MULTIPLEXADOS QUE ESTAN CONECTADOS A CADA UNO DE LOS BUSES DE RESULTADOS. CADA UNO DE LOS REGISTROS DE PROPOSITO GENERAL TAMBIEN TIENE UN PUERTO DE SALIDA QUE ESTA CONECTADO A UN PUERTO DE ENTRADA MULTIPLEXADO DE AL MENOS UNO DE LOS CIRCUITOS COMPUTACIONALES. CADA UNO DE LOS CIRCUITOS COMPUTACIONALES ESTA DEDICADO A AL MENOS UNA FUNCION MATEMATICA UNICA, Y AL MENOS UNO DE LOS CIRCUITOS COMPUTACIONALES INCLUYE AL MENOS UNA FUNCION LOGICA. AL MENOS UNO DE LOS CIRCUITOS COMPUTACIONALES INCLUYE UNA PLURALIDAD DE CIRCUITOS DE PROCESAMIENTO MATEMATICOSY LOGICOS CONCURRENTEMENTE ACCIONABLES, Y UN MULTIPLEXADOR DE SALIDA PARA SELECCIONAR UNA DE LAS SALIDAS RESULTANTES PARA SU TRANSMISION SOBRE SU BUS DE RESULTADOS. LA CPU TAMBIEN INCORPORA UNA PALABRA DE INSTRUCCION MUY LARGA QUE UTILIZA UNA SERIE DE UBICACION DE BITS ASIGNADAS PARA REPRESENTAR LOS CODIGOS DE SELECCION PARA CADA UNO DE LOS COMPONENTES DE LA CPU. ESTOS CODIGOS DE SELECCION SON DIRECTAMENTE TRANSMITIDOS A CADA UNO DE LOS COMPONENTES DE LA CPU MEDIANTE UN CIRCUITO DE CONTROL DE PROGRAMA. SE SUMINISTRA ADEMAS UN CIRCUITO DE CONTROL DE DATOS SEPARADO EN UN DISEÑO DE ESTRUCTURA HARVARD PARA LA CPU.
ES95909225T 1994-01-10 1995-01-10 Ordenador de arquitectura harvard superescalar masivamente multiplexado. Expired - Lifetime ES2148492T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US17925694A 1994-01-10 1994-01-10

Publications (1)

Publication Number Publication Date
ES2148492T3 true ES2148492T3 (es) 2000-10-16

Family

ID=22655833

Family Applications (1)

Application Number Title Priority Date Filing Date
ES95909225T Expired - Lifetime ES2148492T3 (es) 1994-01-10 1995-01-10 Ordenador de arquitectura harvard superescalar masivamente multiplexado.

Country Status (9)

Country Link
US (1) US5655133A (es)
EP (1) EP0739517B1 (es)
JP (1) JPH09507596A (es)
AT (1) ATE195596T1 (es)
CA (1) CA2180855A1 (es)
DE (1) DE69518403T2 (es)
ES (1) ES2148492T3 (es)
SG (1) SG44642A1 (es)
WO (1) WO1995019006A1 (es)

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Also Published As

Publication number Publication date
ATE195596T1 (de) 2000-09-15
US5655133A (en) 1997-08-05
SG44642A1 (en) 1997-12-19
DE69518403D1 (de) 2000-09-21
WO1995019006A1 (en) 1995-07-13
JPH09507596A (ja) 1997-07-29
EP0739517A1 (en) 1996-10-30
CA2180855A1 (en) 1995-07-13
EP0739517B1 (en) 2000-08-16
DE69518403T2 (de) 2001-03-29

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