ES2173861T3 - Conjunto de chips apilados y metado para fabricarlo. - Google Patents

Conjunto de chips apilados y metado para fabricarlo.

Info

Publication number
ES2173861T3
ES2173861T3 ES92111531T ES92111531T ES2173861T3 ES 2173861 T3 ES2173861 T3 ES 2173861T3 ES 92111531 T ES92111531 T ES 92111531T ES 92111531 T ES92111531 T ES 92111531T ES 2173861 T3 ES2173861 T3 ES 2173861T3
Authority
ES
Spain
Prior art keywords
chips
substrate
stacked
connection card
manufacture
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES92111531T
Other languages
English (en)
Inventor
Louis E Gates Jr
Richard K Cochran
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Raytheon Co
Original Assignee
Raytheon Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Raytheon Co filed Critical Raytheon Co
Application granted granted Critical
Publication of ES2173861T3 publication Critical patent/ES2173861T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/36—Assembling printed circuits with other printed circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/533—Cross-sectional shape
    • H10W72/534—Cross-sectional shape being rectangular
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/60—Strap connectors, e.g. thick copper clips for grounding of power devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/834—Interconnections on sidewalls of chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/284—Configurations of stacked chips characterised by structural arrangements for measuring or testing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Wire Bonding (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Dicing (AREA)
  • Credit Cards Or The Like (AREA)

Abstract

DOS O MAS CIRCUITOS INTEGRADOS O CHIPS DE MEMORIA (64-66, 104, 106-108, 116-118, 122-126) SE APILAN SOBRE UN SUBSTRATO DE UN CIRCUITO (72, 100) O SOBRE UNA TARJETA IMPRESA DE CONEXION DE FORMA QUE LOS PLANOS DE LOS CHIPS DESCANSEN HORIZONTALMENTE SOBRE EL SUBSTRATO O TARJETA DE CONEXIONES. LOS CHIPS ESTAN PREFERIBLEMENTE INTERCONECTADOS A LO LARGO DE TODOS SUS BORDES (68) Y POR LO TANTO, PREFERIBLEMENTE POR MEDIO DE UNIONES EN FORMA DE CINTA, AL SUBSTRATO O A LA TARJETA DE CONEXIONES. ESTA DISPOSICION ASI MONTADA SE SELLA HERMETICAMENTE MEDIANTE REVESTIMIENTOS DE PASIVACION Y ENCAPSULACION. DICHOS CHIPS (25) SE ENCUENTRA SOBREDIMENSIONADOS, PARA DISTINGUIRLOS DE LOS CHIPS CONVENCIONALES. ESPECIFICAMENTE, CADA CHIPS ES MAYOR QUE UN CIRCUITO INDIVIDUAL (18, 20), ESTO ES CADA PLAQUETA (24) QUE SE SELECCIONA PARA SER CONFORMADA COMO UN CHIP TIENE UN TAMAÑO QUE ES MAYOR QUE EL CIRCUITO INDIVIDUAL QUE INCORPORA, SUPERPONIENDOSE ASI A LOS CIRCUITOS ADYACENTES.
ES92111531T 1991-07-09 1992-07-08 Conjunto de chips apilados y metado para fabricarlo. Expired - Lifetime ES2173861T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/727,500 US5311401A (en) 1991-07-09 1991-07-09 Stacked chip assembly and manufacturing method therefor

Publications (1)

Publication Number Publication Date
ES2173861T3 true ES2173861T3 (es) 2002-11-01

Family

ID=24922916

Family Applications (1)

Application Number Title Priority Date Filing Date
ES92111531T Expired - Lifetime ES2173861T3 (es) 1991-07-09 1992-07-08 Conjunto de chips apilados y metado para fabricarlo.

Country Status (9)

Country Link
US (1) US5311401A (es)
EP (1) EP0522518B1 (es)
JP (1) JPH0834283B2 (es)
KR (1) KR960003768B1 (es)
AU (1) AU656595B2 (es)
CA (1) CA2073363A1 (es)
DE (1) DE69232611T2 (es)
ES (1) ES2173861T3 (es)
IL (1) IL102397A (es)

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Also Published As

Publication number Publication date
DE69232611D1 (de) 2002-06-27
AU1947592A (en) 1993-01-21
IL102397A (en) 1995-03-30
DE69232611T2 (de) 2003-01-30
AU656595B2 (en) 1995-02-09
US5311401A (en) 1994-05-10
EP0522518A2 (en) 1993-01-13
IL102397A0 (en) 1993-05-13
JPH05259375A (ja) 1993-10-08
KR960003768B1 (ko) 1996-03-22
KR930003308A (ko) 1993-02-24
EP0522518B1 (en) 2002-05-22
EP0522518A3 (en) 1994-11-30
JPH0834283B2 (ja) 1996-03-29
CA2073363A1 (en) 1993-01-10

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