ES8303743A1 - Sistema de proceso de datos para el proceso en paralelo. - Google Patents

Sistema de proceso de datos para el proceso en paralelo.

Info

Publication number
ES8303743A1
ES8303743A1 ES510535A ES510535A ES8303743A1 ES 8303743 A1 ES8303743 A1 ES 8303743A1 ES 510535 A ES510535 A ES 510535A ES 510535 A ES510535 A ES 510535A ES 8303743 A1 ES8303743 A1 ES 8303743A1
Authority
ES
Spain
Prior art keywords
parallel
data
processing system
operating
data processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES510535A
Other languages
English (en)
Other versions
ES510535A0 (es
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of ES8303743A1 publication Critical patent/ES8303743A1/es
Publication of ES510535A0 publication Critical patent/ES510535A0/es
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053—Vector processors
    • G06F15/8076—Details on data register access
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Complex Calculations (AREA)
  • Advance Control (AREA)
  • Multi Processors (AREA)

Abstract

SISTEMA DE PROCESO DE DATOS PARA PROCESO EN PARALELO. INCLUYE VARIAS UNIDADES DE OPERACION, CADA UNA DE LAS CUALES EJECUTA UNA INSTRUCCION DIFERENTE. INCLUYE TAMBIEN DIVERSOS DISPOSITIVOS DE CONTROL DE INSTRUCCION, TALES QUE CADA UNO DE ELLOS COMPRENDE AL MENOS DOS ETAPAS PARA LA LECTURA DE LOS DATOS DE OPERANDO ORIGINALES PROCEDENTES DE UNA MEMORIA LOCAL, Y PARA LA INSCRIPCION DE LOS DATOS DE OPERANDO RESULTANTE EN DICHA MEMORIA. CADA UNO DE ESTOS DISPOSITIVOS EJERCE IGUALMENTE FUNCIONES DE CONTROL DE LA EJECUCION DE DIFERENTES INSTRUCCIONES EN PARALELO.
ES510535A 1981-03-20 1982-03-17 Sistema de proceso de datos para el proceso en paralelo. Granted ES510535A0 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56039536A JPS57155666A (en) 1981-03-20 1981-03-20 Instruction controlling system of vector processor

Publications (2)

Publication Number Publication Date
ES8303743A1 true ES8303743A1 (es) 1983-02-01
ES510535A0 ES510535A0 (es) 1983-02-01

Family

ID=12555764

Family Applications (1)

Application Number Title Priority Date Filing Date
ES510535A Granted ES510535A0 (es) 1981-03-20 1982-03-17 Sistema de proceso de datos para el proceso en paralelo.

Country Status (9)

Country Link
US (1) US4507728A (es)
EP (1) EP0061096B1 (es)
JP (1) JPS57155666A (es)
KR (1) KR860001274B1 (es)
AU (1) AU538595B2 (es)
BR (1) BR8201533A (es)
CA (1) CA1176757A (es)
DE (1) DE3262186D1 (es)
ES (1) ES510535A0 (es)

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US4636942A (en) * 1983-04-25 1987-01-13 Cray Research, Inc. Computer vector multiprocessing control
US4661900A (en) * 1983-04-25 1987-04-28 Cray Research, Inc. Flexible chaining in vector processor with selective use of vector registers as operand and result registers
US4589067A (en) * 1983-05-27 1986-05-13 Analogic Corporation Full floating point vector processor with dynamically configurable multifunction pipelined ALU
JPS6015771A (ja) * 1983-07-08 1985-01-26 Hitachi Ltd ベクトルプロセッサ
JPS6072069A (ja) * 1983-09-28 1985-04-24 Nec Corp ベクトル演算処理装置
JPS60101644A (ja) * 1983-11-07 1985-06-05 Masahiro Sowa ノイマン型コンピュータプログラムを実行するコントロールフローコンピュータ
JPS60134974A (ja) * 1983-12-23 1985-07-18 Hitachi Ltd ベクトル処理装置
JPS60136870A (ja) * 1983-12-26 1985-07-20 Hitachi Ltd ベクトル処理装置
JPS60136875A (ja) * 1983-12-26 1985-07-20 Hitachi Ltd ベクトル演算器
JPS60239871A (ja) * 1984-05-14 1985-11-28 Nec Corp ベクトルデ−タ処理装置
US4809171A (en) * 1984-06-20 1989-02-28 Convex Computer Corporation Concurrent processing of data operands
US4766564A (en) * 1984-08-13 1988-08-23 International Business Machines Corporation Dual putaway/bypass busses for multiple arithmetic units
JPH0769818B2 (ja) * 1984-10-31 1995-07-31 株式会社日立製作所 デ−タ処理装置
JPS61110256A (ja) * 1984-11-02 1986-05-28 Hitachi Ltd 複数の演算部を有するプロセツサ
EP0184791A1 (en) * 1984-12-07 1986-06-18 Nec Corporation Information processing device capable of rapidly processing instructions of different groups
US5255384A (en) * 1985-02-22 1993-10-19 Intergraph Corporation Memory address translation system having modifiable and non-modifiable translation mechanisms
US4860192A (en) * 1985-02-22 1989-08-22 Intergraph Corporation Quadword boundary cache system
US4899275A (en) * 1985-02-22 1990-02-06 Intergraph Corporation Cache-MMU system
US4933835A (en) * 1985-02-22 1990-06-12 Intergraph Corporation Apparatus for maintaining consistency of a cache memory with a primary memory
JPS621067A (ja) * 1985-02-25 1987-01-07 Hitachi Ltd ベクトル処理装置
JPS61202281A (ja) * 1985-03-05 1986-09-08 Fujitsu Ltd パイプライン制御方式
JPH0766329B2 (ja) * 1985-06-14 1995-07-19 株式会社日立製作所 情報処理装置
EP0205193B1 (en) * 1985-06-17 1996-10-23 Nec Corporation Information processing system comprising a register renewal waiting control circuit with renewal register number registering means
US4745545A (en) * 1985-06-28 1988-05-17 Cray Research, Inc. Memory reference control in a multiprocessor
US4754398A (en) * 1985-06-28 1988-06-28 Cray Research, Inc. System for multiprocessor communication using local and common semaphore and information registers
US4873630A (en) * 1985-07-31 1989-10-10 Unisys Corporation Scientific processor to support a host processor referencing common memory
JPH0743648B2 (ja) * 1985-11-15 1995-05-15 株式会社日立製作所 情報処理装置
JPS62120574A (ja) * 1985-11-20 1987-06-01 Fujitsu Ltd ベクトル処理装置
US4839845A (en) * 1986-03-31 1989-06-13 Unisys Corporation Method and apparatus for performing a vector reduction
US5091846A (en) * 1986-10-03 1992-02-25 Intergraph Corporation Cache providing caching/non-caching write-through and copyback modes for virtual addresses and including bus snooping to maintain coherency
US4811214A (en) * 1986-11-14 1989-03-07 Princeton University Multinode reconfigurable pipeline computer
JPS63131230A (ja) * 1986-11-21 1988-06-03 Hitachi Ltd 情報処理装置
US4891753A (en) * 1986-11-26 1990-01-02 Intel Corporation Register scorboarding on a microprocessor chip
JPH0810430B2 (ja) * 1986-11-28 1996-01-31 株式会社日立製作所 情報処理装置
JP2695157B2 (ja) * 1986-12-29 1997-12-24 松下電器産業株式会社 可変パイプラインプロセッサ
NL8700530A (nl) * 1987-03-05 1988-10-03 Philips Nv Pijplijnsysteem met parallelle data-beschrijving.
US4792894A (en) * 1987-03-17 1988-12-20 Unisys Corporation Arithmetic computation modifier based upon data dependent operations for SIMD architectures
JPS63200142U (es) * 1987-06-05 1988-12-23
US4901267A (en) * 1988-03-14 1990-02-13 Weitek Corporation Floating point circuit with configurable number of multiplier cycles and variable divide cycle ratio
EP0340453B1 (en) * 1988-04-01 1997-06-11 Nec Corporation Instruction handling sequence control system
JPH06105460B2 (ja) * 1988-06-07 1994-12-21 富士通株式会社 マルチプロセッサのプロセッサ切換え装置
EP0346031B1 (en) * 1988-06-07 1997-12-29 Fujitsu Limited Vector data processing apparatus
GB8817911D0 (en) * 1988-07-27 1988-09-01 Int Computers Ltd Data processing apparatus
US5142638A (en) * 1989-02-07 1992-08-25 Cray Research, Inc. Apparatus for sharing memory in a multiprocessor system
US5185880A (en) * 1989-06-05 1993-02-09 Matsushita Electric Industrial Co., Ltd. Stored instructions executing type timing signal generating system
US5203002A (en) * 1989-12-27 1993-04-13 Wetzel Glen F System with a multiport memory and N processing units for concurrently/individually executing 2N-multi-instruction-words at first/second transitions of a single clock cycle
US5206952A (en) * 1990-09-12 1993-04-27 Cray Research, Inc. Fault tolerant networking architecture
US5539911A (en) * 1991-07-08 1996-07-23 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US5363495A (en) * 1991-08-26 1994-11-08 International Business Machines Corporation Data processing system with multiple execution units capable of executing instructions out of sequence
US5420815A (en) * 1991-10-29 1995-05-30 Advanced Micro Devices, Inc. Digital multiplication and accumulation system
DE69229212T2 (de) * 1991-10-29 2000-01-20 Advanced Micro Devices, Inc. Datensignalverarbeitungsgerät
JPH0821833B2 (ja) * 1992-07-28 1996-03-04 インターナショナル・ビジネス・マシーンズ・コーポレイション ディジタルオーディオ情報をフィルタする回路及びフィルタされたディジタル信号を生成する方法
US5579527A (en) * 1992-08-05 1996-11-26 David Sarnoff Research Center Apparatus for alternately activating a multiplier and a match unit
US5509129A (en) * 1993-11-30 1996-04-16 Guttag; Karl M. Long instruction word controlling plural independent processor operations
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US5465336A (en) * 1994-06-30 1995-11-07 International Business Machines Corporation Fetch and store buffer that enables out-of-order execution of memory instructions in a data processing system
US5706489A (en) * 1995-10-18 1998-01-06 International Business Machines Corporation Method for a CPU to utilize a parallel instruction execution processing facility for assisting in the processing of the accessed data
US6226706B1 (en) 1997-12-29 2001-05-01 Samsung Electronics Co., Ltd. Rotation bus interface coupling processor buses to memory buses for interprocessor communication via exclusive memory access
US7509486B1 (en) * 1999-07-08 2009-03-24 Broadcom Corporation Encryption processor for performing accelerated computations to establish secure network sessions connections
ATE390788T1 (de) * 1999-10-14 2008-04-15 Bluearc Uk Ltd Vorrichtung und verfahren zur hardware-ausführung oder hardware-beschleunigung von betriebssystemfunktionen
US7149878B1 (en) * 2000-10-30 2006-12-12 Mips Technologies, Inc. Changing instruction set architecture mode by comparison of current instruction execution address with boundary address register values
US7711926B2 (en) * 2001-04-18 2010-05-04 Mips Technologies, Inc. Mapping system and method for instruction set processing
US6826681B2 (en) * 2001-06-18 2004-11-30 Mips Technologies, Inc. Instruction specified register value saving in allocated caller stack or not yet allocated callee stack
US7107439B2 (en) 2001-08-10 2006-09-12 Mips Technologies, Inc. System and method of controlling software decompression through exceptions
US8041735B1 (en) 2002-11-01 2011-10-18 Bluearc Uk Limited Distributed file system and method
US7457822B1 (en) 2002-11-01 2008-11-25 Bluearc Uk Limited Apparatus and method for hardware-based file system
KR20190132741A (ko) 2018-05-21 2019-11-29 삼성중공업 주식회사 부유식 구조물의 스키드 장치
CN113762518B (zh) * 2020-06-02 2024-07-12 中科寒武纪科技股份有限公司 数据处理方法、装置、计算机设备和存储介质
CN111783969A (zh) * 2020-06-30 2020-10-16 中科寒武纪科技股份有限公司 数据处理方法、装置、计算机设备和存储介质

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US3229260A (en) * 1962-03-02 1966-01-11 Ibm Multiprocessing computer system
AT335202B (de) * 1973-08-13 1977-02-25 Ibm Oesterreich Datenverarbeitungsanlage zur parallelen ausfuhrung von verarbeitungsoperationen
SE7505552L (sv) * 1975-05-14 1976-11-15 Ellemtel Utvecklings Ab Sett och anordning att efter varandra avverka databehandlingsinstruktioner i funktionsenheter hos en datamaskin
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Also Published As

Publication number Publication date
BR8201533A (pt) 1983-02-08
JPS57155666A (en) 1982-09-25
EP0061096B1 (en) 1985-02-06
AU8161482A (en) 1982-09-23
EP0061096A1 (en) 1982-09-29
JPS6161436B2 (es) 1986-12-25
US4507728A (en) 1985-03-26
CA1176757A (en) 1984-10-23
KR860001274B1 (ko) 1986-09-04
DE3262186D1 (en) 1985-03-21
KR830009518A (ko) 1983-12-21
AU538595B2 (en) 1984-08-23
ES510535A0 (es) 1983-02-01

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Legal Events

Date Code Title Description
FD1A Patent lapsed

Effective date: 19991130