ES8304675A1 - "un circuito digital de control automatico de ganancia". - Google Patents
"un circuito digital de control automatico de ganancia".Info
- Publication number
- ES8304675A1 ES8304675A1 ES513530A ES513530A ES8304675A1 ES 8304675 A1 ES8304675 A1 ES 8304675A1 ES 513530 A ES513530 A ES 513530A ES 513530 A ES513530 A ES 513530A ES 8304675 A1 ES8304675 A1 ES 8304675A1
- Authority
- ES
- Spain
- Prior art keywords
- gain control
- automatic gain
- control circuit
- digital automatic
- loop
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
- H03G3/3089—Control of digital or coded signals
Landscapes
- Control Of Amplification And Gain Control (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
CIRCUITO DIGITAL DE CONTROL AUTOMATICO DE GANANCIA. EL CIRCUITO TIENE DOS BUCLES DE CONTROL AUTOMATICO DE GANANCIA QUE SE ACTIVAN ALTERNATIVAMENTE. EL PRIMERO DE ELLOS (11) ES DEL TIPO DE ALIMENTACION EN AVANCE, SE ACTIVA CUANDO SE SUMINISTRA INICIALMENTE UNA ENTRADA Y PRODUCE UN FACTOR DE PONDERACION PARA MANTENER CONSTANTE EL NIVEL DE SALIDA DE CONTROL AUTOMATICO DE GANANCIA. EL SEGUNDO BUCLE (12) ES DEL TIPO DE REALIMENTACION, Y FUNCIONA A PARTIR DE UN VALOR PREAJUSTADO, POR SU PROPIO FILTRO DE PASO BAJO, DEL COEFICIENTE DE PONDERACION PRODUCIDO POR EL PRIMER BUCLE.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56100534A JPS583406A (ja) | 1981-06-30 | 1981-06-30 | ディジタル形自動利得制御方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| ES8304675A1 true ES8304675A1 (es) | 1983-03-01 |
| ES513530A0 ES513530A0 (es) | 1983-03-01 |
Family
ID=14276619
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| ES513530A Granted ES513530A0 (es) | 1981-06-30 | 1982-06-28 | "un circuito digital de control automatico de ganancia". |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US4482973A (es) |
| EP (1) | EP0069515B1 (es) |
| JP (1) | JPS583406A (es) |
| CA (1) | CA1198823A (es) |
| DE (1) | DE3273551D1 (es) |
| ES (1) | ES513530A0 (es) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6020611A (ja) * | 1983-07-14 | 1985-02-01 | Fujitsu Ltd | ピ−ク値検出形agc回路 |
| AU560995B2 (en) * | 1984-02-07 | 1987-04-30 | Toshiba, Kabushiki Kaisha | Process control apparatus |
| DE3723383A1 (de) * | 1987-07-15 | 1989-01-26 | Siemens Ag | Schaltender pi-regler mit rueckfuehrung |
| US5321849A (en) * | 1991-05-22 | 1994-06-14 | Southwestern Bell Technology Resources, Inc. | System for controlling signal level at both ends of a transmission link based on a detected valve |
| US5678198A (en) * | 1991-05-22 | 1997-10-14 | Southwestern Bell Technology Resources, Inc. | System for controlling signal level at both ends of a transmission link, based upon a detected value |
| FI106325B (fi) | 1998-11-12 | 2001-01-15 | Nokia Networks Oy | Menetelmä ja laite tehonsäädön ohjaamiseksi |
| US7558391B2 (en) * | 1999-11-29 | 2009-07-07 | Bizjak Karl L | Compander architecture and methods |
| US7190292B2 (en) * | 1999-11-29 | 2007-03-13 | Bizjak Karl M | Input level adjust system and method |
| US6870830B1 (en) | 2000-11-30 | 2005-03-22 | 3Com Corporation | System and method for performing messaging services using a data communications channel in a data network telephone system |
| US7386074B1 (en) | 2003-10-06 | 2008-06-10 | Redpine Signals, Inc. | Digital automatic gain control method and apparatus |
| US8249271B2 (en) | 2007-01-23 | 2012-08-21 | Karl M. Bizjak | Noise analysis and extraction systems and methods |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3983381A (en) * | 1974-12-18 | 1976-09-28 | International Business Machines Corporation | Digital automatic gain control circuit |
| US4213097A (en) * | 1978-10-19 | 1980-07-15 | Racal-Milgo, Inc. | Hybrid automatic gain control circuit |
| US4191995A (en) * | 1979-01-02 | 1980-03-04 | Bell Telephone Laboratories, Incorporated | Digital automatic gain control circuit |
| US4221934A (en) * | 1979-05-11 | 1980-09-09 | Rca Corporation | Compandor for group of FDM signals |
| IT1121030B (it) * | 1979-09-18 | 1986-03-26 | Cselt Centro Studi Lab Telecom | Procedimento e circuito per il controllo automatico del guadagno in apparecchiature elettroniche |
-
1981
- 1981-06-30 JP JP56100534A patent/JPS583406A/ja active Granted
-
1982
- 1982-06-23 CA CA000405867A patent/CA1198823A/en not_active Expired
- 1982-06-25 EP EP82303328A patent/EP0069515B1/en not_active Expired
- 1982-06-25 DE DE8282303328T patent/DE3273551D1/de not_active Expired
- 1982-06-28 ES ES513530A patent/ES513530A0/es active Granted
- 1982-06-28 US US06/393,120 patent/US4482973A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| DE3273551D1 (en) | 1986-11-06 |
| ES513530A0 (es) | 1983-03-01 |
| EP0069515B1 (en) | 1986-10-01 |
| US4482973A (en) | 1984-11-13 |
| JPS583406A (ja) | 1983-01-10 |
| EP0069515A2 (en) | 1983-01-12 |
| CA1198823A (en) | 1985-12-31 |
| JPS6319089B2 (es) | 1988-04-21 |
| EP0069515A3 (en) | 1984-03-07 |
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