FR2286558A1 - Dispositif logique integre programmable - Google Patents
Dispositif logique integre programmableInfo
- Publication number
- FR2286558A1 FR2286558A1 FR7529565A FR7529565A FR2286558A1 FR 2286558 A1 FR2286558 A1 FR 2286558A1 FR 7529565 A FR7529565 A FR 7529565A FR 7529565 A FR7529565 A FR 7529565A FR 2286558 A1 FR2286558 A1 FR 2286558A1
- Authority
- FR
- France
- Prior art keywords
- matrix
- complementary
- transistors
- logic device
- integrated logic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000011159 matrix material Substances 0.000 abstract 7
- 230000000295 complement effect Effects 0.000 abstract 4
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
- H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
- H03K19/17712—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays one of the matrices at least being reprogrammable
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
- H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
Landscapes
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19742446655 DE2446655A1 (de) | 1974-09-30 | 1974-09-30 | Integrierte, programmierbare logikanordnung |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| FR2286558A1 true FR2286558A1 (fr) | 1976-04-23 |
Family
ID=5927138
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| FR7529565A Withdrawn FR2286558A1 (fr) | 1974-09-30 | 1975-09-26 | Dispositif logique integre programmable |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JPS5161257A (fr) |
| BE (1) | BE834023A (fr) |
| DE (1) | DE2446655A1 (fr) |
| FR (1) | FR2286558A1 (fr) |
| IT (1) | IT1042846B (fr) |
| NL (1) | NL7511458A (fr) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0193927A (ja) * | 1987-10-06 | 1989-04-12 | Fujitsu Ltd | プログラム可能な論理回路 |
| JPH03231515A (ja) * | 1990-02-06 | 1991-10-15 | Mitsubishi Electric Corp | プログラマブル論理装置 |
| JPH0435120A (ja) * | 1990-05-25 | 1992-02-05 | Nec Corp | プログラマブル・ロジック・アレイ回路 |
-
1974
- 1974-09-30 DE DE19742446655 patent/DE2446655A1/de active Pending
-
1975
- 1975-09-25 IT IT2762175A patent/IT1042846B/it active
- 1975-09-26 FR FR7529565A patent/FR2286558A1/fr not_active Withdrawn
- 1975-09-29 NL NL7511458A patent/NL7511458A/xx unknown
- 1975-09-30 BE BE160550A patent/BE834023A/fr unknown
- 1975-09-30 JP JP11822075A patent/JPS5161257A/ja active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| NL7511458A (nl) | 1976-04-01 |
| DE2446655A1 (de) | 1976-04-01 |
| IT1042846B (it) | 1980-01-30 |
| BE834023A (fr) | 1976-01-16 |
| JPS5161257A (ja) | 1976-05-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| GB1127687A (en) | Logic circuitry | |
| GB1377126A (en) | Charge couple circuits | |
| JPS6418312A (en) | Four-state input/output control circuit | |
| FR2659810B1 (fr) | Interrupteur statique moyenne tension. | |
| KR900001598B1 (en) | The decoder circuit of semiconductor memory device | |
| EP0685806A4 (fr) | Dispositif a semiconducteur. | |
| GB1483169A (en) | Inverters | |
| GB1483068A (en) | Circuit comprised of insulated gate field effect transistors | |
| GB1426191A (en) | Digital circuits | |
| FR2352449A1 (fr) | Dispositif logique a trois etats en technologie mos complementaire | |
| GB1196216A (en) | A Bistable Circuit | |
| RU95121790A (ru) | Парафазный логический элемент на мдп-транзисторах | |
| KR880008535A (ko) | 3스테이트부 상보형 mos 집적회로 | |
| KR850002174A (ko) | 반도체 집적회로 장치 | |
| DE3865432D1 (de) | Gatterschaltung mit mos-transistoren. | |
| ES406104A1 (es) | Una disposicion de puerta electronica de transferencia de senales. | |
| GB1259237A (fr) | ||
| US3706889A (en) | Multiple-phase logic circuits | |
| SU1707757A1 (ru) | Троичный дизъюнктор на МДП-транзисторах | |
| JPS5636220A (en) | Static type d flip-flop circuit | |
| JPS5531357A (en) | Insulated gate type field effect transistor logic gate circuit | |
| SU405167A1 (ru) | Однофазный инверсный д-триггер | |
| ES380476A1 (es) | Disposicion de circuitos electronicos. | |
| IT1038107B (it) | Circuito logico perfezionato | |
| SU966912A1 (ru) | Элемент "исключающее ИЛИ |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| ST | Notification of lapse |