FR2709207A1 - Procédé de métallisation d'un circuit intégré. - Google Patents

Procédé de métallisation d'un circuit intégré.

Info

Publication number
FR2709207A1
FR2709207A1 FR9402273A FR9402273A FR2709207A1 FR 2709207 A1 FR2709207 A1 FR 2709207A1 FR 9402273 A FR9402273 A FR 9402273A FR 9402273 A FR9402273 A FR 9402273A FR 2709207 A1 FR2709207 A1 FR 2709207A1
Authority
FR
France
Prior art keywords
integrated circuit
metallic layer
opening
metallization process
contact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR9402273A
Other languages
English (en)
Other versions
FR2709207B1 (fr
Inventor
Kuang-Chao Chen
Shaw Tzeng Hsia
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Industrial Technology Research Institute ITRI
Original Assignee
Industrial Technology Research Institute ITRI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Industrial Technology Research Institute ITRI filed Critical Industrial Technology Research Institute ITRI
Publication of FR2709207A1 publication Critical patent/FR2709207A1/fr
Application granted granted Critical
Publication of FR2709207B1 publication Critical patent/FR2709207B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/035—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/047—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by introducing additional elements therein
    • H10W20/049—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by introducing additional elements therein by diffusing alloying elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/42—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a gas or vapour
    • H10P14/44—Physical vapour deposition [PVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Physical Vapour Deposition (AREA)

Abstract

Procédé de métallisation d'un circuit intégré consistant à fournir une couche isolante sur la surface d'un substrat de semi-conducteur, fournir au moins une ouverture pour contact à travers ladite couche isolante vers ledit substrat de semi-conducteur, déposer une couche métallique de connexion sur la surface dudit substrat et à l'intérieur de ladite ouverture pour contact dans laquelle la plus grande partie dudit métal de connexion est dépmosée sur le fond de ladite ouverture pour contact plutôt que sur les côtés de ladite ouverture; pulvériser à froid une couche métallique sur ladite couche métallique de connexion, et pulvériser à chaud une couche métallique sur ladite couche métallique pulvérisée à froid, dans lequel ladite pulvérisation à chaud et à froid sont des opérations continues pour réaliser ladite métallisation dudit circuit intégré.
FR9402273A 1993-08-19 1994-02-28 Procédé de métallisation d'un circuit intégré. Expired - Fee Related FR2709207B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/108,224 US5356836A (en) 1993-08-19 1993-08-19 Aluminum plug process

Publications (2)

Publication Number Publication Date
FR2709207A1 true FR2709207A1 (fr) 1995-02-24
FR2709207B1 FR2709207B1 (fr) 1996-10-25

Family

ID=22320980

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9402273A Expired - Fee Related FR2709207B1 (fr) 1993-08-19 1994-02-28 Procédé de métallisation d'un circuit intégré.

Country Status (5)

Country Link
US (1) US5356836A (fr)
JP (1) JPH0766205A (fr)
KR (1) KR100291284B1 (fr)
DE (1) DE4400726A1 (fr)
FR (1) FR2709207B1 (fr)

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US5883002A (en) * 1996-08-29 1999-03-16 Winbond Electronics Corp. Method of forming contact profile by improving TEOS/BPSG selectivity for manufacturing a semiconductor device
US5985746A (en) * 1996-11-21 1999-11-16 Lsi Logic Corporation Process for forming self-aligned conductive plugs in multiple insulation levels in integrated circuit structures and resulting product
JPH10172969A (ja) * 1996-12-06 1998-06-26 Nec Corp 半導体装置の製造方法
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US6395629B1 (en) 1997-04-16 2002-05-28 Stmicroelectronics, Inc. Interconnect method and structure for semiconductor devices
KR100241506B1 (ko) * 1997-06-23 2000-03-02 김영환 반도체 소자의 금속 배선 형성 방법
US5994206A (en) * 1997-10-06 1999-11-30 Advanced Micro Devices, Inc. Method of forming a high conductivity metal interconnect using metal gettering plug and system performing the method
US6365514B1 (en) 1997-12-23 2002-04-02 Intel Corporation Two chamber metal reflow process
US6307267B1 (en) * 1997-12-26 2001-10-23 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method thereof
US5994213A (en) * 1998-02-09 1999-11-30 Taiwan Semiconductor Manufacturing Company, Ltd. Aluminum plug process
US6130156A (en) * 1998-04-01 2000-10-10 Texas Instruments Incorporated Variable doping of metal plugs for enhanced reliability
KR20000004358A (ko) * 1998-06-30 2000-01-25 김영환 반도체 소자의 배선 구조
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US6207568B1 (en) * 1998-11-27 2001-03-27 Taiwan Semiconductor Manufacturing Company Ionized metal plasma (IMP) method for forming (111) oriented aluminum containing conductor layer
TW409356B (en) * 1999-03-11 2000-10-21 United Microelectronics Corp Manufacture method of inner connects
US6627542B1 (en) * 1999-07-12 2003-09-30 Applied Materials, Inc. Continuous, non-agglomerated adhesion of a seed layer to a barrier layer
US6080657A (en) * 1999-07-16 2000-06-27 Taiwan Semiconductor Manufacturing Company Method of reducing AlCu hillocks
KR100434188B1 (ko) * 2001-08-28 2004-06-04 삼성전자주식회사 장벽 금속층 적층 방법
US6943105B2 (en) * 2002-01-18 2005-09-13 International Business Machines Corporation Soft metal conductor and method of making
KR100455380B1 (ko) * 2002-02-27 2004-11-06 삼성전자주식회사 다층 배선 구조를 구비한 반도체 소자 및 그 제조 방법
US7056820B2 (en) * 2003-11-20 2006-06-06 International Business Machines Corporation Bond pad
JP2011091242A (ja) * 2009-10-23 2011-05-06 Elpida Memory Inc 半導体装置の製造方法
US9941160B2 (en) * 2013-07-25 2018-04-10 Globalfoundries Singapore Pte. Ltd. Integrated circuits having device contacts and methods for fabricating the same
KR101550526B1 (ko) * 2014-02-21 2015-09-04 에스티에스반도체통신 주식회사 클러스터형 반도체 제조장치 및 이를 이용한 반도체 소자 제조방법
JP2017183396A (ja) * 2016-03-29 2017-10-05 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
CN116397205A (zh) * 2023-03-30 2023-07-07 华虹半导体(无锡)有限公司 避免静电吸盘边缘损伤的热铝工艺方法
CN119170566A (zh) * 2024-10-29 2024-12-20 无锡邑文微电子科技股份有限公司 一种热铝填孔的方法及溅射装置

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EP0483669A2 (fr) * 1990-10-24 1992-05-06 Sumitomo Metal Industries, Ltd. Procédé de formation d'une couche mince et dispositifs semiconducteurs
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EP0499241A1 (fr) * 1991-02-12 1992-08-19 Applied Materials, Inc. Procédé de pulvérisation d'une couche d'aluminium sur des plaquettes échelonnées
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EP0514103A1 (fr) * 1991-05-14 1992-11-19 STMicroelectronics, Inc. Procédé de fabrication d'une barrière en métal pour contacts sous-micromiques

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Publication number Priority date Publication date Assignee Title
EP0430403A2 (fr) * 1989-11-30 1991-06-05 STMicroelectronics, Inc. Méthode de fabrication des contacts intercalés
EP0483669A2 (fr) * 1990-10-24 1992-05-06 Sumitomo Metal Industries, Ltd. Procédé de formation d'une couche mince et dispositifs semiconducteurs
EP0488628A2 (fr) * 1990-11-30 1992-06-03 STMicroelectronics, Inc. Méthode de fabrication d'un trou de liaison/contact empilées en aluminium pour des interconnexions à multi-couches
EP0499241A1 (fr) * 1991-02-12 1992-08-19 Applied Materials, Inc. Procédé de pulvérisation d'une couche d'aluminium sur des plaquettes échelonnées
EP0512296A1 (fr) * 1991-04-19 1992-11-11 Siemens Aktiengesellschaft Procédé de dépôt, à haute temperature, de conducteurs dans des trous plus profonds que larges
EP0514103A1 (fr) * 1991-05-14 1992-11-19 STMicroelectronics, Inc. Procédé de fabrication d'une barrière en métal pour contacts sous-micromiques

Also Published As

Publication number Publication date
KR950006997A (ko) 1995-03-21
FR2709207B1 (fr) 1996-10-25
DE4400726A1 (de) 1995-02-23
KR100291284B1 (ko) 2001-11-30
US5356836A (en) 1994-10-18
JPH0766205A (ja) 1995-03-10

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