FR2787212B1 - Circuit pour remettre a l'etat initial une paire de bus de donnees d'un dispositif de memoire a semiconducteur - Google Patents

Circuit pour remettre a l'etat initial une paire de bus de donnees d'un dispositif de memoire a semiconducteur

Info

Publication number
FR2787212B1
FR2787212B1 FR9915524A FR9915524A FR2787212B1 FR 2787212 B1 FR2787212 B1 FR 2787212B1 FR 9915524 A FR9915524 A FR 9915524A FR 9915524 A FR9915524 A FR 9915524A FR 2787212 B1 FR2787212 B1 FR 2787212B1
Authority
FR
France
Prior art keywords
resetting
pair
circuit
memory device
semiconductor memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR9915524A
Other languages
English (en)
Other versions
FR2787212A1 (fr
Inventor
Hiroyuki Sugamoto
Takaaki Furuyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of FR2787212A1 publication Critical patent/FR2787212A1/fr
Application granted granted Critical
Publication of FR2787212B1 publication Critical patent/FR2787212B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 

Landscapes

  • Engineering & Computer Science (AREA)
  • Databases & Information Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
FR9915524A 1998-12-10 1999-12-09 Circuit pour remettre a l'etat initial une paire de bus de donnees d'un dispositif de memoire a semiconducteur Expired - Fee Related FR2787212B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP35125698 1998-12-10
JP11197401A JP2000231791A (ja) 1998-12-10 1999-07-12 半導体記憶装置及びデータバスのリセット方法

Publications (2)

Publication Number Publication Date
FR2787212A1 FR2787212A1 (fr) 2000-06-16
FR2787212B1 true FR2787212B1 (fr) 2003-09-26

Family

ID=26510344

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9915524A Expired - Fee Related FR2787212B1 (fr) 1998-12-10 1999-12-09 Circuit pour remettre a l'etat initial une paire de bus de donnees d'un dispositif de memoire a semiconducteur

Country Status (5)

Country Link
US (2) US6198680B1 (fr)
JP (1) JP2000231791A (fr)
DE (1) DE19958268A1 (fr)
FR (1) FR2787212B1 (fr)
TW (1) TW454203B (fr)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3447640B2 (ja) 1999-12-28 2003-09-16 日本電気株式会社 半導体記憶装置
JP2004198367A (ja) * 2002-12-20 2004-07-15 Fujitsu Ltd 半導体装置及びその試験方法
US20050149792A1 (en) * 2002-12-20 2005-07-07 Fujitsu Limited Semiconductor device and method for testing the same
KR100524950B1 (ko) * 2003-02-28 2005-11-01 삼성전자주식회사 전류 소모를 줄이는 인터페이싱 회로
JP2004355760A (ja) 2003-05-30 2004-12-16 Renesas Technology Corp データ記憶回路
US7283418B2 (en) * 2005-07-26 2007-10-16 Micron Technology, Inc. Memory device and method having multiple address, data and command buses
JP5475889B2 (ja) * 2010-08-25 2014-04-16 ルネサスエレクトロニクス株式会社 データ処理装置およびデータ処理システム
US11908542B2 (en) * 2019-12-23 2024-02-20 Intel Corporation Energy efficient memory array with optimized burst read and write data access
JP2024075828A (ja) * 2022-11-24 2024-06-05 ルネサスエレクトロニクス株式会社 Ｄｒａｍ回路

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2615011B2 (ja) * 1986-06-13 1997-05-28 株式会社日立製作所 半導体記憶回路
JPS6376193A (ja) * 1986-09-19 1988-04-06 Fujitsu Ltd 半導体記憶装置
JPH0762955B2 (ja) * 1989-05-15 1995-07-05 株式会社東芝 ダイナミック型ランダムアクセスメモリ
GB9007788D0 (en) * 1990-04-06 1990-06-06 Foss Richard C Dynamic memory bitline precharge scheme
US5257226A (en) 1991-12-17 1993-10-26 Sgs-Thomson Microelectronics, Inc. Integrated circuit with self-biased differential data lines
US5295104A (en) 1991-12-17 1994-03-15 Sgs-Thomson Microelectronics, Inc. Integrated circuit with precharged internal data bus
EP0547892B1 (fr) * 1991-12-17 1998-10-28 STMicroelectronics, Inc. Circuit intégré avec des lignes de données différentielles auto polarisées
JP2658768B2 (ja) * 1992-10-19 1997-09-30 日本電気株式会社 ダイナミックｒａｍ
JP2906957B2 (ja) * 1993-12-15 1999-06-21 日本電気株式会社 半導体メモリ装置
KR0171954B1 (ko) * 1995-06-30 1999-03-30 김주용 데이타 버스 구동 회로
JP3088340B2 (ja) * 1997-06-18 2000-09-18 日本電気アイシーマイコンシステム株式会社 半導体記憶装置

Also Published As

Publication number Publication date
DE19958268A1 (de) 2000-06-21
JP2000231791A (ja) 2000-08-22
FR2787212A1 (fr) 2000-06-16
TW454203B (en) 2001-09-11
US6462997B2 (en) 2002-10-08
US20010001261A1 (en) 2001-05-17
US6198680B1 (en) 2001-03-06

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Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20081020