FR2987700B1 - Memoire non volatile comprenant des mini caissons a potentiel flottant - Google Patents

Memoire non volatile comprenant des mini caissons a potentiel flottant

Info

Publication number
FR2987700B1
FR2987700B1 FR1253330A FR1253330A FR2987700B1 FR 2987700 B1 FR2987700 B1 FR 2987700B1 FR 1253330 A FR1253330 A FR 1253330A FR 1253330 A FR1253330 A FR 1253330A FR 2987700 B1 FR2987700 B1 FR 2987700B1
Authority
FR
France
Prior art keywords
trenches
substrate
sgci
niso
mini
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR1253330A
Other languages
English (en)
Other versions
FR2987700A1 (fr
Inventor
Rosa Francesco La
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Rousset SAS
Original Assignee
STMicroelectronics Rousset SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Rousset SAS filed Critical STMicroelectronics Rousset SAS
Priority to FR1253330A priority Critical patent/FR2987700B1/fr
Priority to US13/786,197 priority patent/US8940604B2/en
Priority to US13/786,213 priority patent/US8901634B2/en
Publication of FR2987700A1 publication Critical patent/FR2987700A1/fr
Application granted granted Critical
Publication of FR2987700B1 publication Critical patent/FR2987700B1/fr
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/016—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including vertical IGFETs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

L'invention concerne un circuit intégré (IC) comprenant une mémoire non volatile sur un substrat semi-conducteur (WF, PW). Le circuit intégré comprend une couche d'isolation dopée (NISO) implantée dans la profondeur du substrat, des tranchées conductrices isolées (SGCi,i+i) atteignant la couche d'isolation (NISO), formant des grilles (SGC) de transistors de sélection (ST41, ST42) de cellules mémoire (C41, C42), des tranchées d'isolation (STI) perpendiculaires aux tranchées conductrice (SGCi,i+i), et atteignant la couche d'isolation (NISO), et des lignes conductrices (CGi, CGi+i) parallèles aux tranchées conductrices (SGCi,i+i), s'étendant sur le substrat (PW) et formant des grilles de contrôle (CG) de transistors à accumulation de charges (FGT41, FGT42) de cellules mémoire (C41, C42). les tranchées d'isolation et les tranchées conductrices isolées délimitent dans le substrat une pluralité de mini caissons (MPW1, MPW2, MPW3) isolés électriquement les uns des autres, ayant chacun un potentiel électrique flottant, et comprenant chacun deux cellules mémoire.
FR1253330A 2012-03-05 2012-04-11 Memoire non volatile comprenant des mini caissons a potentiel flottant Expired - Fee Related FR2987700B1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR1253330A FR2987700B1 (fr) 2012-03-05 2012-04-11 Memoire non volatile comprenant des mini caissons a potentiel flottant
US13/786,197 US8940604B2 (en) 2012-03-05 2013-03-05 Nonvolatile memory comprising mini wells at a floating potential
US13/786,213 US8901634B2 (en) 2012-03-05 2013-03-05 Nonvolatile memory cells with a vertical selection gate of variable depth

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1251968A FR2987697A1 (fr) 2012-03-05 2012-03-05 Procede de fabrication d'une memoire non volatile
FR1253330A FR2987700B1 (fr) 2012-03-05 2012-04-11 Memoire non volatile comprenant des mini caissons a potentiel flottant

Publications (2)

Publication Number Publication Date
FR2987700A1 FR2987700A1 (fr) 2013-09-06
FR2987700B1 true FR2987700B1 (fr) 2014-03-14

Family

ID=46197545

Family Applications (2)

Application Number Title Priority Date Filing Date
FR1251968A Pending FR2987697A1 (fr) 2012-03-05 2012-03-05 Procede de fabrication d'une memoire non volatile
FR1253330A Expired - Fee Related FR2987700B1 (fr) 2012-03-05 2012-04-11 Memoire non volatile comprenant des mini caissons a potentiel flottant

Family Applications Before (1)

Application Number Title Priority Date Filing Date
FR1251968A Pending FR2987697A1 (fr) 2012-03-05 2012-03-05 Procede de fabrication d'une memoire non volatile

Country Status (1)

Country Link
FR (2) FR2987697A1 (fr)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3012673B1 (fr) 2013-10-31 2017-04-14 St Microelectronics Rousset Memoire programmable par injection de porteurs chauds et procede de programmation d'une telle memoire
FR3012672B1 (fr) 2013-10-31 2017-04-14 Stmicroelectronics Rousset Cellule memoire comprenant des grilles de controle horizontale et verticale non auto-alignees
FR3017746B1 (fr) 2014-02-18 2016-05-27 Stmicroelectronics Rousset Cellule memoire verticale ayant un implant drain-source flottant non auto-aligne
FR3021806B1 (fr) * 2014-05-28 2017-09-01 St Microelectronics Sa Procede de programmation d'une cellule memoire non volatile comprenant une grille de transistor de selection partagee
FR3030883B1 (fr) * 2014-12-17 2017-12-22 Stmicroelectronics Rousset Cellule memoire a grille de selection verticale formee dans un substrat de type fdsoi
FR3054723A1 (fr) * 2016-07-27 2018-02-02 Stmicroelectronics (Rousset) Sas Cellule-memoire eeprom compacte avec zone d'injection tunnel reduite
FR3071355B1 (fr) 2017-09-20 2019-08-30 Stmicroelectronics (Rousset) Sas Cellule-memoire eeprom compacte
CN114076565B (zh) * 2020-08-18 2025-09-09 上海华力微电子有限公司 Cmos图像传感器转移管垂直栅极深度检测方法
US12289884B2 (en) 2021-05-21 2025-04-29 Stmicroelectronics (Rousset) Sas Integrated circuit comprising at least one bipolar transistor and a corresponding method of production

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW546778B (en) * 2001-04-20 2003-08-11 Koninkl Philips Electronics Nv Two-transistor flash cell
US6894339B2 (en) * 2003-01-02 2005-05-17 Actrans System Inc. Flash memory with trench select gate and fabrication process
US8139408B2 (en) * 2006-09-05 2012-03-20 Semiconductor Components Industries, L.L.C. Scalable electrically eraseable and programmable memory

Also Published As

Publication number Publication date
FR2987697A1 (fr) 2013-09-06
FR2987700A1 (fr) 2013-09-06

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