FR3021803B1 - Cellules memoire jumelles accessibles individuellement en lecture - Google Patents

Cellules memoire jumelles accessibles individuellement en lecture

Info

Publication number
FR3021803B1
FR3021803B1 FR1454893A FR1454893A FR3021803B1 FR 3021803 B1 FR3021803 B1 FR 3021803B1 FR 1454893 A FR1454893 A FR 1454893A FR 1454893 A FR1454893 A FR 1454893A FR 3021803 B1 FR3021803 B1 FR 3021803B1
Authority
FR
France
Prior art keywords
twinly
memory cells
individually reading
accessible individually
accessible
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR1454893A
Other languages
English (en)
Other versions
FR3021803A1 (fr
Inventor
Rosa Francesco La
Stephan Niel
Arnaud Regnier
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Rousset SAS
Original Assignee
STMicroelectronics Rousset SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Rousset SAS filed Critical STMicroelectronics Rousset SAS
Priority to FR1454893A priority Critical patent/FR3021803B1/fr
Priority to US14/671,606 priority patent/US9653470B2/en
Priority to CN201520251293.0U priority patent/CN204966056U/zh
Priority to CN201510196923.3A priority patent/CN105280229B/zh
Priority to CN201910456430.7A priority patent/CN110265077B/zh
Publication of FR3021803A1 publication Critical patent/FR3021803A1/fr
Application granted granted Critical
Publication of FR3021803B1 publication Critical patent/FR3021803B1/fr
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0411—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having floating gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/681—Floating-gate IGFETs having only two programming levels
    • H10D30/683—Floating-gate IGFETs having only two programming levels programmed by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/689—Vertical floating-gate IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
    • H10D30/6892—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Non-Volatile Memory (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Read Only Memory (AREA)
FR1454893A 2014-05-28 2014-05-28 Cellules memoire jumelles accessibles individuellement en lecture Expired - Fee Related FR3021803B1 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
FR1454893A FR3021803B1 (fr) 2014-05-28 2014-05-28 Cellules memoire jumelles accessibles individuellement en lecture
US14/671,606 US9653470B2 (en) 2014-05-28 2015-03-27 Individually read-accessible twin memory cells
CN201520251293.0U CN204966056U (zh) 2014-05-28 2015-04-23 非易失性存储器以及在半导体芯片上的集成电路
CN201510196923.3A CN105280229B (zh) 2014-05-28 2015-04-23 单独地读出可访问的配对存储器单元
CN201910456430.7A CN110265077B (zh) 2014-05-28 2015-04-23 单独地读出可访问的配对存储器单元

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR1454893A FR3021803B1 (fr) 2014-05-28 2014-05-28 Cellules memoire jumelles accessibles individuellement en lecture

Publications (2)

Publication Number Publication Date
FR3021803A1 FR3021803A1 (fr) 2015-12-04
FR3021803B1 true FR3021803B1 (fr) 2017-10-13

Family

ID=51168254

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1454893A Expired - Fee Related FR3021803B1 (fr) 2014-05-28 2014-05-28 Cellules memoire jumelles accessibles individuellement en lecture

Country Status (3)

Country Link
US (1) US9653470B2 (fr)
CN (3) CN204966056U (fr)
FR (1) FR3021803B1 (fr)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3021804B1 (fr) 2014-05-28 2017-09-01 Stmicroelectronics Rousset Cellule memoire non volatile duale comprenant un transistor d'effacement
FR3021803B1 (fr) 2014-05-28 2017-10-13 Stmicroelectronics Rousset Cellules memoire jumelles accessibles individuellement en lecture
FR3025353B1 (fr) * 2014-09-03 2016-09-09 Stmicroelectronics Rousset Memoire non volatile composite a effacement par page ou par mot
FR3036221B1 (fr) 2015-05-11 2017-04-28 Stmicroelectronics Rousset Structure d'interconnexion de cellules memoire jumelles
FR3049380B1 (fr) * 2016-03-22 2018-11-23 Stmicroelectronics (Rousset) Sas Amelioration des performances en lecture d'un dispositif de memoire non volatile, en particulier un dispositif de memoire non volatile avec transistor de selection enterre
JP6739327B2 (ja) * 2016-12-27 2020-08-12 ルネサスエレクトロニクス株式会社 半導体装置
TWI632558B (zh) * 2017-05-01 2018-08-11 卡比科技有限公司 非揮發性記憶體裝置及其操作方法
US11011533B2 (en) 2018-01-10 2021-05-18 Ememory Technology Inc. Memory structure and programing and reading methods thereof
JP2019179799A (ja) * 2018-03-30 2019-10-17 ルネサスエレクトロニクス株式会社 半導体記憶装置
US11705403B2 (en) * 2020-12-03 2023-07-18 Micron Technology, Inc. Memory device including support structures
US11568934B2 (en) * 2021-04-06 2023-01-31 Micron Technology, Inc. Multi-gate transistors, apparatus having multi-gate transistors, and methods of forming multi-gate transistors
US20250070018A1 (en) * 2023-08-21 2025-02-27 Taiwan Semiconductor Manufacturing Company Ltd. Anti-fuse cells with backside power rails
FR3155116A1 (fr) * 2023-11-02 2025-05-09 Stmicroelectronics International N.V. circuit intégré comportant une cellule mémoire et procédé de fabrication correspondant
FR3158586A1 (fr) * 2024-01-19 2025-07-25 Stmicroelectronics International N.V. Procédé de fabrication d’un circuit intégré et circuit intégré correspondant
EP4669048A1 (fr) * 2024-06-19 2025-12-24 STMicroelectronics International N.V. Circuit de mémoire non volatile et procédé de fabrication d'un tel circuit de mémoire

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US7126188B2 (en) * 2004-05-27 2006-10-24 Skymedi Corporation Vertical split gate memory cell and manufacturing method thereof
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FR3021803B1 (fr) * 2014-05-28 2017-10-13 Stmicroelectronics Rousset Cellules memoire jumelles accessibles individuellement en lecture
FR3021804B1 (fr) 2014-05-28 2017-09-01 Stmicroelectronics Rousset Cellule memoire non volatile duale comprenant un transistor d'effacement

Also Published As

Publication number Publication date
CN110265077B (zh) 2023-05-12
CN105280229B (zh) 2019-07-16
CN110265077A (zh) 2019-09-20
FR3021803A1 (fr) 2015-12-04
CN105280229A (zh) 2016-01-27
US20150348981A1 (en) 2015-12-03
CN204966056U (zh) 2016-01-13
US9653470B2 (en) 2017-05-16

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