FR3085538B1 - Tranche soi et son procede de production - Google Patents

Tranche soi et son procede de production Download PDF

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Publication number
FR3085538B1
FR3085538B1 FR1909701A FR1909701A FR3085538B1 FR 3085538 B1 FR3085538 B1 FR 3085538B1 FR 1909701 A FR1909701 A FR 1909701A FR 1909701 A FR1909701 A FR 1909701A FR 3085538 B1 FR3085538 B1 FR 3085538B1
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France
Prior art keywords
wafer
support substrate
production process
insulating layer
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1909701A
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English (en)
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FR3085538A1 (fr
Inventor
Yoshihiro Koga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumco Corp
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Sumco Corp
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Publication date
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Publication of FR3085538A1 publication Critical patent/FR3085538A1/fr
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Publication of FR3085538B1 publication Critical patent/FR3085538B1/fr
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/25—Arrangements for cooling characterised by their materials
    • H10W40/253—Semiconductors
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/36—Carbides
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • C30B33/04—After-treatment of single crystals or homogeneous polycrystalline material with defined structure using electric or magnetic fields or particle radiation
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • C30B33/06—Joining of crystals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H10P10/12—Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates
    • H10P10/126—Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates characterised by the composition of the bonding layer, e.g. dopant concentration or stoichiometry
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/24—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using chemical vapour deposition [CVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3408—Silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3451—Structure
    • H10P14/3452—Microstructure
    • H10P14/3454—Amorphous

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Recrystallisation Techniques (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Formation Of Insulating Films (AREA)
  • Element Separation (AREA)

Abstract

L’invention concerne une tranche SOI 1 présentant une forte conductivité thermique. La tranche SOI 1 comporte une tranche de silicium formant substrat support 10, une couche active 21 composée de silicium monocristallin sur la tranche de silicium formant substrat support 10, et une couche isolante enterrée 30 placée entre la tranche de silicium formant substrat support 10 et la couche active 21 ; et la couche isolante enterrée 30 comporte une couche isolante 31 composée soit de SiC monocristallin, soit de SiC amorphe, et une couche d’assemblage amorphe 35.
FR1909701A 2018-09-05 2019-09-03 Tranche soi et son procede de production Active FR3085538B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2018-165749 2018-09-05
JP2018165749A JP7024668B2 (ja) 2018-09-05 2018-09-05 Ｓｏｉウェーハ及びその製造方法

Publications (2)

Publication Number Publication Date
FR3085538A1 FR3085538A1 (fr) 2020-03-06
FR3085538B1 true FR3085538B1 (fr) 2021-10-22

Family

ID=69684248

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1909701A Active FR3085538B1 (fr) 2018-09-05 2019-09-03 Tranche soi et son procede de production

Country Status (2)

Country Link
JP (1) JP7024668B2 (fr)
FR (1) FR3085538B1 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7487659B2 (ja) * 2020-12-25 2024-05-21 株式会社Sumco Ｓｏｉウェーハの製造方法
FR3135820B1 (fr) * 2022-05-18 2024-04-26 Commissariat Energie Atomique Procédé de transfert d'une couche depuis un substrat source vers un substrat destination
FR3135819B1 (fr) 2022-05-18 2024-04-26 Commissariat Energie Atomique Procédé de transfert d'une couche depuis un substrat source vers un substrat destination
FR3141557A1 (fr) * 2022-10-27 2024-05-03 Soitec Procédé de formation d’une couche de carbure de silicium
FR3165103A1 (fr) * 2024-07-25 2026-01-30 Commissariat A L' Energie Atomique Et Aux Energies Alternatives Procédé de collage covalent par diffusion atomique pour former une interface de collage conductrice

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02206118A (ja) * 1989-02-06 1990-08-15 Hitachi Ltd 半導体素子
JP2608351B2 (ja) 1990-08-03 1997-05-07 キヤノン株式会社 半導体部材及び半導体部材の製造方法
JP5532527B2 (ja) * 2006-08-03 2014-06-25 株式会社デンソー Ｓｏｉ基板およびその製造方法
US8536629B2 (en) * 2009-02-24 2013-09-17 Nec Corporation Semiconductor device and method for manufacturing the same
JP5644096B2 (ja) * 2009-11-30 2014-12-24 ソニー株式会社 接合基板の製造方法及び固体撮像装置の製造方法
JP6061251B2 (ja) * 2013-07-05 2017-01-18 株式会社豊田自動織機 半導体基板の製造方法
JP6210152B2 (ja) * 2014-04-10 2017-10-11 富士電機株式会社 半導体基板の処理方法及び該処理方法を用いる半導体装置の製造方法
JP2016063099A (ja) 2014-09-19 2016-04-25 株式会社 日立パワーデバイス 半導体装置
JP6500378B2 (ja) * 2014-09-22 2019-04-17 株式会社Sumco 貼合せＳｉＣウェーハの製造方法及び貼合せＳｉＣウェーハ
JP6344622B2 (ja) 2016-07-29 2018-06-20 三菱重工工作機械株式会社 基材接合方法
JP2018018997A (ja) 2016-07-29 2018-02-01 三菱重工工作機械株式会社 基材接合装置及びこれを使用する基材接合方法
CN107958839B (zh) * 2016-10-18 2020-09-29 上海新昇半导体科技有限公司 晶圆键合方法及其键合装置

Also Published As

Publication number Publication date
JP7024668B2 (ja) 2022-02-24
JP2020038916A (ja) 2020-03-12
FR3085538A1 (fr) 2020-03-06

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