FR3089370B1 - Dispositif de génération de signaux analogiques - Google Patents

Dispositif de génération de signaux analogiques Download PDF

Info

Publication number
FR3089370B1
FR3089370B1 FR1872049A FR1872049A FR3089370B1 FR 3089370 B1 FR3089370 B1 FR 3089370B1 FR 1872049 A FR1872049 A FR 1872049A FR 1872049 A FR1872049 A FR 1872049A FR 3089370 B1 FR3089370 B1 FR 3089370B1
Authority
FR
France
Prior art keywords
digital
clock signal
register
input
frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1872049A
Other languages
English (en)
Other versions
FR3089370A1 (fr
Inventor
Grégory Wagner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Teledyne e2v Semiconductors SAS
Original Assignee
Teledyne e2v Semiconductors SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to FR1872049A priority Critical patent/FR3089370B1/fr
Application filed by Teledyne e2v Semiconductors SAS filed Critical Teledyne e2v Semiconductors SAS
Priority to JP2021530796A priority patent/JP7449288B2/ja
Priority to CN201980078697.5A priority patent/CN113169743B/zh
Priority to PCT/EP2019/081587 priority patent/WO2020109041A1/fr
Priority to KR1020217017272A priority patent/KR102797912B1/ko
Priority to US17/286,571 priority patent/US11528032B2/en
Priority to CA3117276A priority patent/CA3117276A1/fr
Priority to EP19805282.1A priority patent/EP3888248A1/fr
Publication of FR3089370A1 publication Critical patent/FR3089370A1/fr
Application granted granted Critical
Publication of FR3089370B1 publication Critical patent/FR3089370B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66Digital/analogue converters
    • H03M1/662Multiplexed conversion systems
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66Digital/analogue converters
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66Digital/analogue converters
    • H03M1/74Simultaneous conversion
    • H03M1/80Simultaneous conversion using weighted impedances
    • H03M1/802Simultaneous conversion using weighted impedances using capacitors, e.g. neuron-mos transistors, charge coupled devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

Dispositif de génération de signaux analogiques comprenant un convertisseur numérique-analogique comprenant au moins une entrée numérique et une sortie analogique, un circuit de génération d’un premier signal d’horloge de fréquence fs, et un registre numérique configuré de manière à recevoir en entrée et stocker N bits représentatifs d’un signal analogique de sortie du convertisseur, N étant un entier supérieur ou égal à 1, et à recevoir le premier signal d’horloge, le registre comprenant pour chaque bit deux sorties numériques complémentaires, caractérisé en ce qu’il comprend un circuit de génération d’un second signal d’horloge de fréquence m x fs, avec m un entier supérieur à 1, et N circuits multiplexeurs, placés entre les sorties du registre numérique et les entrées du convertisseur et configurés de manière à recevoir chacun, sur une entrée de commande, le second signal d’horloge et à recevoir chacun, sur une entrée de données, des signaux issus de deux sorties numériques du registre correspondant au même bit d’entrée du registre, de telle sorte que la fréquence des signaux sortant des circuits multiplexeurs soit 2 x m x fs. Figure pour l’abrégé : Fig. 1
FR1872049A 2018-11-29 2018-11-29 Dispositif de génération de signaux analogiques Active FR3089370B1 (fr)

Priority Applications (8)

Application Number Priority Date Filing Date Title
FR1872049A FR3089370B1 (fr) 2018-11-29 2018-11-29 Dispositif de génération de signaux analogiques
CN201980078697.5A CN113169743B (zh) 2018-11-29 2019-11-18 用于产生模拟信号的装置
PCT/EP2019/081587 WO2020109041A1 (fr) 2018-11-29 2019-11-18 Dispositif de generation de signaux analogiques
KR1020217017272A KR102797912B1 (ko) 2018-11-29 2019-11-18 아날로그 신호를 생성하는 디바이스
JP2021530796A JP7449288B2 (ja) 2018-11-29 2019-11-18 アナログ信号生成装置
US17/286,571 US11528032B2 (en) 2018-11-29 2019-11-18 Device for generating analogue signals
CA3117276A CA3117276A1 (fr) 2018-11-29 2019-11-18 Dispositif de generation de signaux analogiques
EP19805282.1A EP3888248A1 (fr) 2018-11-29 2019-11-18 Dispositif de generation de signaux analogiques

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR1872049A FR3089370B1 (fr) 2018-11-29 2018-11-29 Dispositif de génération de signaux analogiques

Publications (2)

Publication Number Publication Date
FR3089370A1 FR3089370A1 (fr) 2020-06-05
FR3089370B1 true FR3089370B1 (fr) 2020-11-27

Family

ID=68210830

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1872049A Active FR3089370B1 (fr) 2018-11-29 2018-11-29 Dispositif de génération de signaux analogiques

Country Status (8)

Country Link
US (1) US11528032B2 (fr)
EP (1) EP3888248A1 (fr)
JP (1) JP7449288B2 (fr)
KR (1) KR102797912B1 (fr)
CN (1) CN113169743B (fr)
CA (1) CA3117276A1 (fr)
FR (1) FR3089370B1 (fr)
WO (1) WO2020109041A1 (fr)

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4092639A (en) * 1976-01-06 1978-05-30 Precision Monolithics, Inc. Digital to analog converter with complementary true current outputs
JPS63224521A (ja) * 1987-03-13 1988-09-19 Nippon Precision Saakitsutsu Kk D/a変換装置
JPH02306722A (ja) * 1989-05-22 1990-12-20 Pioneer Electron Corp D/a変換装置
JP2589809B2 (ja) * 1989-06-12 1997-03-12 松下電器産業株式会社 D/a変換器
JPH06164400A (ja) * 1992-11-16 1994-06-10 Kenwood Corp サンプリング周波数変換装置
US7190751B1 (en) * 2001-06-11 2007-03-13 Lsi Logic Corporation Multi-stage filter circuit and digital signal processing circuit employing the same
JP2004032501A (ja) * 2002-06-27 2004-01-29 Pioneer Electronic Corp デジタル信号変換装置及び方法
US6690313B1 (en) * 2002-10-17 2004-02-10 The Boeing Company Digital-to-analog upconverter
US7042379B2 (en) * 2004-07-30 2006-05-09 Rockwell Scientific Licensing, Llc Return-to-zero current switching digital-to-analog converter
JP2007027921A (ja) * 2005-07-13 2007-02-01 Agilent Technol Inc 信号発生装置の調整方法、および、信号発生装置
US7504976B1 (en) * 2007-01-31 2009-03-17 Lockheed Martin Corporation Direct radio frequency generation using power digital-to-analog conversion
US7796971B2 (en) 2007-03-15 2010-09-14 Analog Devices, Inc. Mixer/DAC chip and method
JP5071282B2 (ja) 2008-07-15 2012-11-14 ソニー株式会社 ビット選択回路
JP5086449B2 (ja) * 2009-01-29 2012-11-28 日本電信電話株式会社 電流スイッチ・セルおよびディジタル/アナログ変換器
KR101086218B1 (ko) * 2009-05-14 2011-11-23 주식회사 실리콘웍스 디지털 아날로그 변환기
EP2487797B1 (fr) * 2011-02-11 2014-04-09 Dialog Semiconductor GmbH CNA d'ajustage pour arriver à une non-linéarité différentiel minimale
FR2981813B1 (fr) * 2011-10-21 2015-01-16 E2V Semiconductors Convertisseur numerique-analogique
US8698663B2 (en) * 2012-08-29 2014-04-15 Telefonaktiebolaget L M Ericsson (Publ) Digital analog converter
US8659458B1 (en) 2012-10-11 2014-02-25 Teledyne Scientific & Imaging, Llc Multiple return-to-zero current switching digital-to-analog converter for RF signal generation
FR3024930B1 (fr) * 2014-08-12 2019-08-09 Stmicroelectronics Sa Liaison serie a haut debit
US9419636B1 (en) * 2015-04-09 2016-08-16 Xilinx, Inc. Clocked current-steering circuit for a digital-to-analog converter
GB2541861A (en) 2015-05-29 2017-03-08 Mqa Ltd Digital to analogue conversion
CA2996399C (fr) * 2015-08-27 2019-04-02 Nippon Telegraph And Telephone Corporation Dispositif de generation de signal
CN107104750B (zh) * 2017-04-25 2018-10-16 电子科技大学 一种基于多dac并行结构的信号源的同步方法
US10069508B1 (en) * 2017-08-23 2018-09-04 Avago Technologies General Ip (Singapore) Pte. Ltd. Multiplexer circuit for a digital to analog converter

Also Published As

Publication number Publication date
JP2022523285A (ja) 2022-04-22
CA3117276A1 (fr) 2020-06-04
CN113169743A (zh) 2021-07-23
FR3089370A1 (fr) 2020-06-05
KR20210095877A (ko) 2021-08-03
US20210344351A1 (en) 2021-11-04
KR102797912B1 (ko) 2025-04-17
JP7449288B2 (ja) 2024-03-13
CN113169743B (zh) 2025-03-11
WO2020109041A1 (fr) 2020-06-04
EP3888248A1 (fr) 2021-10-06
US11528032B2 (en) 2022-12-13

Similar Documents

Publication Publication Date Title
US4181967A (en) Digital apparatus approximating multiplication of analog signal by sine wave signal and method
CN101911499B (zh) 用于在采样率转换系统中计算内插因子的方法和装置
CN105519133B (zh) 用于mems电容式换能器的信号处理
TW200629282A (en) Method and apparatus for high-speed input sampling
TW200801891A (en) Dynamic timing adjustment in a circuit device
WO2004044757A3 (fr) Procede et appareil d'acquisition de donnees
JPH03502995A (ja) 対数極信号処理
ATE538535T1 (de) Digitale frequenzgeregelte verzögerungsleitung
WO2008114700A1 (fr) Appareil de mesure, procédé de mesure, appareil de contrôle, dispositif électronique et programme
CN105262503A (zh) 一种基于群延时校准的多径时延产生装置及方法
MY130620A (en) Dft leakage removal for non-coherently sampled signals.
GB2320378B (en) Universal input data sampling circuit
FR3089370B1 (fr) Dispositif de génération de signaux analogiques
KR850004819A (ko) 승산 회로
JPS5767327A (en) Error testing device
Kolankar et al. FPGA Implementation of QPSK modulator by using Hardware Co-simulation
TW200741237A (en) Calibration device, calibration method, test apparatus and test method
JP2009519448A5 (fr)
FR2433267A1 (fr) Appareil pour recevoir, emmagasiner et fournir des sequences de signaux numeriques
JP2002084659A (ja) 電力系統解析シミュレータ
GB2470313A (en) Circuit testing
KR940020666A (ko) 복조회로 및 그것을 사용한 통신장치(a demodulation circuit and a communication apparatus using it)
Marvasti Reply to" Comment on parseval relationship of nonuniform samples of one and two-dimensional signals"
WO2005006551A3 (fr) Convertisseur de voies de donnees multiples a alignement automatique destine aux systemes a horloges multiples
RU2186456C1 (ru) Устройство для моделирования сигналов произвольной формы

Legal Events

Date Code Title Description
PLFP Fee payment

Year of fee payment: 2

PLSC Publication of the preliminary search report

Effective date: 20200605

PLFP Fee payment

Year of fee payment: 3

PLFP Fee payment

Year of fee payment: 4

PLFP Fee payment

Year of fee payment: 5

PLFP Fee payment

Year of fee payment: 6

PLFP Fee payment

Year of fee payment: 7

PLFP Fee payment

Year of fee payment: 8