HK46191A - Multiple data path cpu architecture - Google Patents

Multiple data path cpu architecture

Info

Publication number
HK46191A
HK46191A HK461/91A HK46191A HK46191A HK 46191 A HK46191 A HK 46191A HK 461/91 A HK461/91 A HK 461/91A HK 46191 A HK46191 A HK 46191A HK 46191 A HK46191 A HK 46191A
Authority
HK
Hong Kong
Prior art keywords
register
parity
bus
special function
cpu
Prior art date
Application number
HK461/91A
Other languages
English (en)
French (fr)
Inventor
Robert Whiting Horst
Shannon Joseph Lynch
Cirillo Lino Costantino
John Martin Beirne
Original Assignee
Tandem Computers Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tandem Computers Incorporated filed Critical Tandem Computers Incorporated
Publication of HK46191A publication Critical patent/HK46191A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3893—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator
    • G06F9/3895—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros
    • G06F9/3897—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros with adaptable data path

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Executing Machine-Instructions (AREA)
  • Multi Processors (AREA)
  • Advance Control (AREA)
  • Image Processing (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Hardware Redundancy (AREA)
  • Control By Computers (AREA)
  • Catalysts (AREA)
  • Transition And Organic Metals Composition Catalysts For Addition Polymerization (AREA)
  • Dram (AREA)
  • Electrotherapy Devices (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Communication Control (AREA)
  • Logic Circuits (AREA)

Claims (1)

  1. CPU-Architektur zur Benutzung in einem Datenverarbeitungssystem, in dem eine Anweisung bewirkt, daß Rechengrößen, während der Ausführung eines Mikrocode-Wortes verarbeitet werden, beinhaltend
    -ein Arithmetik-Logikmittel (10) in einem ersten Datenweg (18, 20) zurAusführung arithmetisch-logischer Operationen an Rechengrößen,
    -mindestens ein selektives Funktionsmittel (12a bis 12n) in einem zweiten Datenweg (26, 28) zur gleichzeitig mit den arithmetisch-logischen Operationen erfolgenden Ausführung von Operationen an Rechengrößen,
    -mehrere erste Speichermittel (34, 36, 38, 40, 42, 44) zur Speicherung von Rechengrößen für die Verarbeitung durch die Arithmetik-Logikmittel (10) und durch die selektiven Funktionsmittel (12a bis 12n),
    -mehrere erste Auswahl-Logikmittel (22, 24, 30, 32) zur selektiven Verbindung von einem der ersten Speichermittel (34, 36, 38, 40, 42, 44) mit dem Arithmetik-Logikmittel (10) und von einem der ersten Speichermittel (34, 36, 38, 40, 42, 44) mit den selektiven Funktionsmitteln (12a bis 12n),
    -eine erste Rückübertragungsleitung (14) zur Rückführung von Ergebnissen einer Operation des Arithmetik-Logikmittels (10) zu mindestens einem der Speichermittel (34, 36, 38, 40, 42, 44),
    -eine zweite Rückübertragungsleitung (16) zur Rückführung von Ergebnissen einer Operation der selektiven Funktionsmittel (12a bis 12n) zu mindestens einem der ersten Speichermittel (34, 36, 38, 40, 42, 44),
    -mindestens einem zweiten Speichermittel (46), das mit mindestens einem der ersten Speichermittel (34, 36, 38, 40, 42, 44) verbunden ist, um Rechengrößen für die Verarbeitung durch das arithmetik-Logikmittel (10) und durch die selektiven Funktionsmittel (12a bis 12n) zu speichern und um die Rechengrößen den ersten Speichermitteln (34, 36, 38, 40, 42, 44) zuzuführen, und
    -mindestens einem zweiten Auswahl-Logikmittel (52, 54), das mit mindestens einem der ersten Speichermittel (34, 36, 38, 40, 42, 44) verbunden ist, um eine von mehreren Datenquellen mit den ersten Speichermitteln (34, 36, 38, 40, 42, 44) selektiv zu verbinden.
HK461/91A 1983-09-29 1991-06-11 Multiple data path cpu architecture HK46191A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/537,877 US4800486A (en) 1983-09-29 1983-09-29 Multiple data patch CPU architecture

Publications (1)

Publication Number Publication Date
HK46191A true HK46191A (en) 1991-06-21

Family

ID=24144474

Family Applications (1)

Application Number Title Priority Date Filing Date
HK461/91A HK46191A (en) 1983-09-29 1991-06-11 Multiple data path cpu architecture

Country Status (19)

Country Link
US (1) US4800486A (de)
EP (1) EP0136179B1 (de)
JP (1) JPH0752386B2 (de)
KR (1) KR920004059B1 (de)
AT (1) ATE58794T1 (de)
AU (1) AU574387B2 (de)
BR (1) BR8404918A (de)
CA (1) CA1215783A (de)
DE (1) DE3483669D1 (de)
DK (1) DK165202C (de)
FI (1) FI85428C (de)
HK (1) HK46191A (de)
IE (1) IE56554B1 (de)
IL (1) IL73106A (de)
IN (1) IN162545B (de)
MX (1) MX157907A (de)
NO (1) NO168497C (de)
NZ (1) NZ209663A (de)
ZA (1) ZA847524B (de)

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US5032986A (en) * 1987-07-28 1991-07-16 Texas Instruments Incorporated Data processing device with parallel circular addressing hardware
JPH01255031A (ja) * 1988-04-05 1989-10-11 Matsushita Electric Ind Co Ltd 演算処理装置
US5109497A (en) * 1989-01-27 1992-04-28 Hughes Aircraft Company Arithmetic element controller for controlling data, control and micro store memories
EP0547240B1 (de) * 1991-07-08 2000-01-12 Seiko Epson Corporation Risc-mikroprozessorarchitektur mit schnellem unterbrechungs- und ausnahmemodus
US5961629A (en) * 1991-07-08 1999-10-05 Seiko Epson Corporation High performance, superscalar-based computer system with out-of-order instruction execution
US5539911A (en) 1991-07-08 1996-07-23 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
KR100299691B1 (ko) 1991-07-08 2001-11-22 구사마 사부로 확장가능알아이에스씨마이크로프로세서구조
US5438668A (en) 1992-03-31 1995-08-01 Seiko Epson Corporation System and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computer
JP3644959B2 (ja) 1992-09-29 2005-05-11 セイコーエプソン株式会社 マイクロプロセッサシステム
US6735685B1 (en) 1992-09-29 2004-05-11 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
US5648733A (en) * 1995-11-01 1997-07-15 Lsi Logic Corporation Scan compatible 3-state bus control
US7669083B2 (en) * 2007-09-11 2010-02-23 International Business Machines Corporation System and method for re-shuffling test case instruction orders for processor design verification and validation
US7992059B2 (en) 2007-09-11 2011-08-02 International Business Machines Corporation System and method for testing a large memory area during processor design verification and validation
US8099559B2 (en) * 2007-09-11 2012-01-17 International Business Machines Corporation System and method for generating fast instruction and data interrupts for processor design verification and validation
US8006221B2 (en) * 2007-09-11 2011-08-23 International Business Machines Corporation System and method for testing multiple processor modes for processor design verification and validation
US8019566B2 (en) * 2007-09-11 2011-09-13 International Business Machines Corporation System and method for efficiently testing cache congruence classes during processor design verification and validation
US20090070570A1 (en) * 2007-09-11 2009-03-12 Shubhodeep Roy Choudhury System and Method for Efficiently Handling Interrupts
US7966521B2 (en) * 2008-07-14 2011-06-21 International Business Machines Corporation Light weight and high throughput test case generation methodology for testing cache/TLB intervention and diagnostics
US9153295B2 (en) * 2012-10-04 2015-10-06 Texas Instruments Incorporated Register bank cross path connection method in a multi core processor system

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Also Published As

Publication number Publication date
EP0136179A2 (de) 1985-04-03
FI85428B (fi) 1991-12-31
JPS60167028A (ja) 1985-08-30
AU3359684A (en) 1985-04-04
ZA847524B (en) 1985-06-26
FI843781L (fi) 1985-03-30
NO168497B (no) 1991-11-18
KR850002906A (ko) 1985-05-20
BR8404918A (pt) 1985-08-20
ATE58794T1 (de) 1990-12-15
US4800486A (en) 1989-01-24
EP0136179A3 (en) 1986-12-30
MX157907A (es) 1988-12-20
JPH0752386B2 (ja) 1995-06-05
NO168497C (no) 1992-02-26
DK462584A (da) 1985-03-30
NO843891L (no) 1985-04-01
DE3483669D1 (de) 1991-01-10
IE842461L (en) 1985-03-29
DK165202C (da) 1993-03-15
DK462584D0 (da) 1984-09-27
IL73106A (en) 1988-04-29
DK165202B (da) 1992-10-19
KR920004059B1 (ko) 1992-05-23
NZ209663A (en) 1989-01-06
IE56554B1 (en) 1991-09-11
IL73106A0 (en) 1984-12-31
AU574387B2 (en) 1988-07-07
EP0136179B1 (de) 1990-11-28
IN162545B (de) 1988-06-11
CA1215783A (en) 1986-12-23
FI85428C (fi) 1992-04-10
FI843781A0 (fi) 1984-09-26

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Legal Events

Date Code Title Description
PC Patent ceased (i.e. patent has lapsed due to the failure to pay the renewal fee)