HK46191A - Multiple data path cpu architecture - Google Patents

Multiple data path cpu architecture

Info

Publication number
HK46191A
HK46191A HK461/91A HK46191A HK46191A HK 46191 A HK46191 A HK 46191A HK 461/91 A HK461/91 A HK 461/91A HK 46191 A HK46191 A HK 46191A HK 46191 A HK46191 A HK 46191A
Authority
HK
Hong Kong
Prior art keywords
register
parity
bus
special function
cpu
Prior art date
Application number
HK461/91A
Other languages
German (de)
English (en)
Inventor
Robert Whiting Horst
Shannon Joseph Lynch
Cirillo Lino Costantino
John Martin Beirne
Original Assignee
Tandem Computers Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tandem Computers Incorporated filed Critical Tandem Computers Incorporated
Publication of HK46191A publication Critical patent/HK46191A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3893—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator
    • G06F9/3895—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros
    • G06F9/3897—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros with adaptable data path

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Executing Machine-Instructions (AREA)
  • Multi Processors (AREA)
  • Advance Control (AREA)
  • Image Processing (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Hardware Redundancy (AREA)
  • Control By Computers (AREA)
  • Catalysts (AREA)
  • Transition And Organic Metals Composition Catalysts For Addition Polymerization (AREA)
  • Dram (AREA)
  • Electrotherapy Devices (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Communication Control (AREA)
  • Logic Circuits (AREA)

Claims (1)

  1. Architecture d'une unité centrale de traitement CPU pour emploi dans un système de traitement des données, dans laquelle une instruction fait en sorte que des opérandes sont traités au cours de l'exécution d'un mot de microcode, comportant:
    des moyens arithmétiques et logiques (10) sur un premier chemin de données (18, 20) pour effectuer des opérations arithmétiques et logiques sur les opérandes, .
    au moins un moyen de fonction sélectionnable (12a-12n), sur un second chemin de données (26, 28), pour effectuer des opérations sur les opérandes simultanément avec les opérations arithmétiques et logiques,
    une pluralité de moyens formant premier registre (34, 36, 38, 40, 42, 44) pour contenir les opérandes à traiter par lesdits moyens arithmétiques et logiques (10) et par lesdits moyens de fonction sélectionnables (12a-12n),
    une pluralité de premiers moyens logiques sélectifs (22, 24, 30, 32) pour relier sélectivement l'un desdits moyens formant premier registre (34, 36, 38, 40, 42, 44) auxdits moyens arithmétiques et logiques (10) et l'un desdits moyens formant premier registre (34, 36, 38, 40, 42, 44) auxdits moyens de fonction sélectionnables (12a-12n),
    des moyens (14) formant premier bus de renvoi pour renvoyer les résultats d'une opération desdits moyens arithmétiques et logiques (10) à au moins l'un desdits moyens formant premier registre (34, 36, 38, 40, 42, 44),
    des moyens (16) formant second bus de renvoi pour renvoyer les résultats d'une opération desdits moyens de fonction sélectionnables (12a-12n) à au moins l'un desdits moyens formant premier registre (34, 36, 38, 40, 42, 44),
    au moins un moyen formant second registre (46) relié à au moins l'un desdits moyens formant premier registre (34, 36, 38, 40, 42, 44) pour contenir les opérandes à traiter par lesdits moyens arithmétiques et logiques (10) et par lesdits moyens de fonction sélectionnables (12a-12n) et pour renvoyer sélectivement lesdits opérandes auxdits moyens formant premier registre (34, 36, 38, 40, 42, 44), et
    au moins un second moyen logique sélectif (52, 54) relié à au moins l'un desdits moyens formant premier registre pour relier sélectivement l'une d'une pluralité de sources de données auxdits moyens formant premier registre.
HK461/91A 1983-09-29 1991-06-11 Multiple data path cpu architecture HK46191A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/537,877 US4800486A (en) 1983-09-29 1983-09-29 Multiple data patch CPU architecture

Publications (1)

Publication Number Publication Date
HK46191A true HK46191A (en) 1991-06-21

Family

ID=24144474

Family Applications (1)

Application Number Title Priority Date Filing Date
HK461/91A HK46191A (en) 1983-09-29 1991-06-11 Multiple data path cpu architecture

Country Status (19)

Country Link
US (1) US4800486A (fr)
EP (1) EP0136179B1 (fr)
JP (1) JPH0752386B2 (fr)
KR (1) KR920004059B1 (fr)
AT (1) ATE58794T1 (fr)
AU (1) AU574387B2 (fr)
BR (1) BR8404918A (fr)
CA (1) CA1215783A (fr)
DE (1) DE3483669D1 (fr)
DK (1) DK165202C (fr)
FI (1) FI85428C (fr)
HK (1) HK46191A (fr)
IE (1) IE56554B1 (fr)
IL (1) IL73106A (fr)
IN (1) IN162545B (fr)
MX (1) MX157907A (fr)
NO (1) NO168497C (fr)
NZ (1) NZ209663A (fr)
ZA (1) ZA847524B (fr)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB8401807D0 (en) * 1984-01-24 1984-02-29 Int Computers Ltd Pipelined data processing apparatus
US4891754A (en) * 1987-07-02 1990-01-02 General Datacomm Inc. Microinstruction sequencer for instructing arithmetic, logical and data move operations in a conditional manner
US5032986A (en) * 1987-07-28 1991-07-16 Texas Instruments Incorporated Data processing device with parallel circular addressing hardware
JPH01255031A (ja) * 1988-04-05 1989-10-11 Matsushita Electric Ind Co Ltd 演算処理装置
US5109497A (en) * 1989-01-27 1992-04-28 Hughes Aircraft Company Arithmetic element controller for controlling data, control and micro store memories
EP0547240B1 (fr) * 1991-07-08 2000-01-12 Seiko Epson Corporation Architecture risc de microprocesseur avec mode d'interruption et d'exception rapide
US5961629A (en) * 1991-07-08 1999-10-05 Seiko Epson Corporation High performance, superscalar-based computer system with out-of-order instruction execution
US5539911A (en) 1991-07-08 1996-07-23 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
KR100299691B1 (ko) 1991-07-08 2001-11-22 구사마 사부로 확장가능알아이에스씨마이크로프로세서구조
US5438668A (en) 1992-03-31 1995-08-01 Seiko Epson Corporation System and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computer
JP3644959B2 (ja) 1992-09-29 2005-05-11 セイコーエプソン株式会社 マイクロプロセッサシステム
US6735685B1 (en) 1992-09-29 2004-05-11 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
US5648733A (en) * 1995-11-01 1997-07-15 Lsi Logic Corporation Scan compatible 3-state bus control
US7669083B2 (en) * 2007-09-11 2010-02-23 International Business Machines Corporation System and method for re-shuffling test case instruction orders for processor design verification and validation
US7992059B2 (en) 2007-09-11 2011-08-02 International Business Machines Corporation System and method for testing a large memory area during processor design verification and validation
US8099559B2 (en) * 2007-09-11 2012-01-17 International Business Machines Corporation System and method for generating fast instruction and data interrupts for processor design verification and validation
US8006221B2 (en) * 2007-09-11 2011-08-23 International Business Machines Corporation System and method for testing multiple processor modes for processor design verification and validation
US8019566B2 (en) * 2007-09-11 2011-09-13 International Business Machines Corporation System and method for efficiently testing cache congruence classes during processor design verification and validation
US20090070570A1 (en) * 2007-09-11 2009-03-12 Shubhodeep Roy Choudhury System and Method for Efficiently Handling Interrupts
US7966521B2 (en) * 2008-07-14 2011-06-21 International Business Machines Corporation Light weight and high throughput test case generation methodology for testing cache/TLB intervention and diagnostics
US9153295B2 (en) * 2012-10-04 2015-10-06 Texas Instruments Incorporated Register bank cross path connection method in a multi core processor system

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1426749A (en) * 1973-06-05 1976-03-03 Burroughs Corp Micro programme data processor having parallel instruction flow streams for plural level of subinstruction sets
US3900723A (en) * 1974-05-28 1975-08-19 Control Data Corp Apparatus for controlling computer pipelines for arithmetic operations on vectors
JPS513743A (fr) * 1974-06-28 1976-01-13 Hitachi Ltd
US4041461A (en) * 1975-07-25 1977-08-09 International Business Machines Corporation Signal analyzer system
GB1506972A (en) * 1976-02-06 1978-04-12 Int Computers Ltd Data processing systems
IT1059493B (it) * 1976-04-22 1982-05-31 Olivetti & Co Spa Dispositivo per cambiare l ambiente di lavoro di un calcolatore
US4128880A (en) * 1976-06-30 1978-12-05 Cray Research, Inc. Computer vector register processing
US4075704A (en) * 1976-07-02 1978-02-21 Floating Point Systems, Inc. Floating point data processor for high speech operation
US4179734A (en) * 1976-07-02 1979-12-18 Floating Point Systems, Inc. Floating point data processor having fast access memory means
GB1527289A (en) * 1976-08-17 1978-10-04 Int Computers Ltd Data processing systems
JPS5847042B2 (ja) * 1977-03-08 1983-10-20 株式会社日立製作所 異常検知方法
US4101960A (en) * 1977-03-29 1978-07-18 Burroughs Corporation Scientific processor
FR2413712A1 (fr) * 1977-12-30 1979-07-27 Ibm France Microprocesseur specialise pour le calcul de la somme de produits de deux operandes complexes
JPS6024985B2 (ja) * 1978-08-31 1985-06-15 富士通株式会社 デ−タ処理方式
US4251885A (en) * 1979-03-09 1981-02-17 International Business Machines Corporation Checking programmed controller operation
US4253183A (en) * 1979-05-02 1981-02-24 Ncr Corporation Method and apparatus for diagnosing faults in a processor having a pipeline architecture
US4298935A (en) * 1979-10-05 1981-11-03 Honeywell Information Systems Inc. Interface circuit for coupling an automated maintenance system to a CPU
US4315313A (en) * 1979-12-27 1982-02-09 Ncr Corporation Diagnostic circuitry in a data processor
US4392200A (en) * 1980-01-28 1983-07-05 Digital Equipment Corporation Cached multiprocessor system with pipeline timing
CA1174370A (fr) * 1980-05-19 1984-09-11 Hidekazu Matsumoto Unite de traitement de donnees avec operandes a traitement "pipeline"
US4376976A (en) * 1980-07-31 1983-03-15 Sperry Corporation Overlapped macro instruction control system
KR860001434B1 (ko) * 1980-11-21 1986-09-24 후지쑤 가부시끼가이샤 데이타 처리시 스템
US4414669A (en) * 1981-07-23 1983-11-08 General Electric Company Self-testing pipeline processors
JPS58114274A (ja) * 1981-12-28 1983-07-07 Hitachi Ltd デ−タ処理装置
JPS59111569A (ja) * 1982-12-17 1984-06-27 Hitachi Ltd ベクトル処理装置
US4594655A (en) * 1983-03-14 1986-06-10 International Business Machines Corporation (k)-Instructions-at-a-time pipelined processor for parallel execution of inherently sequential instructions
US4618956A (en) * 1983-09-29 1986-10-21 Tandem Computers Incorporated Method of operating enhanced alu test hardware
US4574344A (en) * 1983-09-29 1986-03-04 Tandem Computers Incorporated Entry control store for enhanced CPU pipeline performance

Also Published As

Publication number Publication date
EP0136179A2 (fr) 1985-04-03
FI85428B (fi) 1991-12-31
JPS60167028A (ja) 1985-08-30
AU3359684A (en) 1985-04-04
ZA847524B (en) 1985-06-26
FI843781L (fi) 1985-03-30
NO168497B (no) 1991-11-18
KR850002906A (ko) 1985-05-20
BR8404918A (pt) 1985-08-20
ATE58794T1 (de) 1990-12-15
US4800486A (en) 1989-01-24
EP0136179A3 (en) 1986-12-30
MX157907A (es) 1988-12-20
JPH0752386B2 (ja) 1995-06-05
NO168497C (no) 1992-02-26
DK462584A (da) 1985-03-30
NO843891L (no) 1985-04-01
DE3483669D1 (de) 1991-01-10
IE842461L (en) 1985-03-29
DK165202C (da) 1993-03-15
DK462584D0 (da) 1984-09-27
IL73106A (en) 1988-04-29
DK165202B (da) 1992-10-19
KR920004059B1 (ko) 1992-05-23
NZ209663A (en) 1989-01-06
IE56554B1 (en) 1991-09-11
IL73106A0 (en) 1984-12-31
AU574387B2 (en) 1988-07-07
EP0136179B1 (fr) 1990-11-28
IN162545B (fr) 1988-06-11
CA1215783A (fr) 1986-12-23
FI85428C (fi) 1992-04-10
FI843781A0 (fi) 1984-09-26

Similar Documents

Publication Publication Date Title
EP0136179B1 (fr) Architecture d'unité processeur central à voie de données multiple
US5185872A (en) System for executing different cycle instructions by selectively bypassing scoreboard register and canceling the execution of conditionally issued instruction if needed resources are busy
US5640524A (en) Method and apparatus for chaining vector instructions
EP0679988B1 (fr) Circuit à détecter une gamme
EP1124181B1 (fr) Appareil de traitement de données
US5958044A (en) Multicycle NOP
US4541045A (en) Microprocessor architecture employing efficient operand and instruction addressing
US7603497B2 (en) Method and apparatus to launch write queue read data in a microprocessor recovery unit
EP0024288A2 (fr) Système de traitement d'information comportant au moins deux processeurs avec une mémoire commune
DE69623461T2 (de) Koordination von befehlsausgabe in einem parallelen befehlsverarbeitungssystem
US5335333A (en) Guess mechanism for faster address calculation in a pipelined microprocessor
US5544337A (en) Vector processor having registers for control by vector resisters
US6393550B1 (en) Method and apparatus for pipeline streamlining where resources are immediate or certainly retired
US5805849A (en) Data processing system and method for using an unique identifier to maintain an age relationship between executing instructions
EP0136183A2 (fr) Dispositif de mémoire de commande pour le fonctionnement de pipeline d'un CPU
US4085450A (en) Performance invarient execution unit for non-communicative instructions
US6023751A (en) Computer system and method for evaluating predicates and Boolean expressions
US5598547A (en) Vector processor having functional unit paths of differing pipeline lengths
US6378061B1 (en) Apparatus for issuing instructions and reissuing a previous instructions by recirculating using the delay circuit
US5142685A (en) Pipeline circuit for timing adjustment of irregular valid and invalid data
US5729729A (en) System for fast trap generation by creation of possible trap masks from early trap indicators and selecting one mask using late trap indicators
JPS61114341A (ja) 処理システム
US6351807B1 (en) Data processing system utilizing multiple resister loading for fast domain switching
GB2269924A (en) Register scoreboarding in a pipelined microprocessor
Mori et al. Implementation and Evaluation of Oki 32-bit Microprocessor 032

Legal Events

Date Code Title Description
PC Patent ceased (i.e. patent has lapsed due to the failure to pay the renewal fee)